公开(公告)号：US11271011B2

公开(公告)日：2022-03-08

申请号：US16924377

申请日：2020-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shyam Agarwal ,  Abhishek Ghosh ,  Parvinder Kumar Rana

IPC: H01L27/118 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092

Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.

公开(公告)号：US10803929B2

公开(公告)日：2020-10-13

申请号：US16857269

申请日：2020-04-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Lava Kumar Pulluru ,  Parvinder Kumar Rana ,  Akash Kumar Gupta ,  Gayatri Nair

IPC: G11C11/419 ,  G11C11/4097 ,  G11C7/10 ,  G11C7/18 ,  G11C8/12 ,  G11C11/418 ,  G11C7/12

Abstract: A static random-access memory (SRAM) system using a virtual banking architecture includes a processor communicatively coupled to an SRAM, and a plurality of circuits disposed in the SRAM and operated under control of the processor. The circuits include a divide circuit, a select circuit disposed in the divide circuit, and a local input/output circuit. The divide circuit divides a bank into first and second bit cell arrays, in which the first bit cell array and/or the second bit cell array includes at least one bit line. The select circuit is connected between the first and second bit cell arrays, and the select circuit selects one of the first and second bit cell arrays according to a predefined select logic. The local input/output circuit is connected to the select circuit and generates an output according to one or more predefined operations of the local input/output circuit.

公开(公告)号：US10748932B2

公开(公告)日：2020-08-18

申请号：US16124946

申请日：2018-09-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shyam Agarwal ,  Abhishek Ghosh ,  Parvinder Kumar Rana

IPC: H01L27/118 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092

Abstract: Inventive concepts describe a method for high performance standard cell design techniques in FinFET based library using LLE. Inventive concepts describe a fabrication process using a standard FinFET cell layout having double diffusion breaks (DDBs) and single diffusion breaks (SDBs). According to one example embodiment, the method comprises of removing one or more fingers of a P-type FinFet (PFET) from a standard FinFET cell layout. After removing the one or more fingers, a Half-Double Diffusion Break (Half-DDB) is introduced on a N-type FinFET (NFET) side inside a cell boundary using a cut-poly layer. The cut-poly layer not only isolates the PFET and NFET gates and also becomes an integral part of hybrid structure. Further, the removed one or more fingers of PFET gates are converted to two floating PFET gates by shorting a drain terminal and a source terminal of the PFET gate to a common power net.

公开(公告)号：US10715118B2

公开(公告)日：2020-07-14

申请号：US16101789

申请日：2018-08-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shyam Agarwal ,  Sandeep B V ,  Shreyas Samraksh Jayaprakash ,  Abhishek Kumar Ghosh ,  Parvinder Kumar Rana

IPC: G11C11/41 ,  H03K3/3562 ,  H01L27/11 ,  H03K19/017 ,  H03K3/012

Abstract: Various example embodiments herein disclose a flip-flop including a master latch comprising one of: a plurality of P-type metal-oxide-semiconductor (PMOS) and a plurality of N-type metal-oxide-semiconductor (NMOS). A slave latch includes one of: a plurality of PMOS and a plurality of NMOS. An inverted clock signal input is communicatively connected with the master latch and the slave latch. The master latch includes a single pre-charge node. The single pre-charge node sets up a data capture path in the flip flop. Data is stored in the master latch and the slave latch via the pre-charge node.

公开(公告)号：US20200067507A1

公开(公告)日：2020-02-27

申请号：US16363292

申请日：2019-03-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sajal Mittal ,  Jaskaran Singh Bhatia ,  Rajeela Deshpande ,  Parvinder Kumar Rana ,  Nikhila C M ,  Abhishek Ghosh ,  Rahul Kataria

IPC: H03K19/00 ,  H03K3/037 ,  H03K3/012 ,  H03K19/0185

Abstract: A method and a flip-flop for designing low power integrated circuits (IC's). The method includes receiving at least one of a clock signal, a data signal, and a complimentary data signal. The complimentary data signal is produced by an input data inverter present in the flip-flop. Further, the method includes generating at least one master internal signal based on the received at least one of the clock signal, the data signal, and the complimentary data signal, when the clock signal is at a low logic level. Further, the method includes generating at least one slave internal signal based on at least one of the received clock signal and the generated at least one master internal signal, when the clock signal is at a high logic level. Further, the method includes generating an output signal based on the generated at least one slave internal signal.

公开(公告)号：US20190058461A1

公开(公告)日：2019-02-21

申请号：US16101789

申请日：2018-08-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shyam AGARWAL ,  Sandeep B V ,  Shreyas Samraksh Jayaprakash ,  Abhishek Kumar Ghosh ,  Parvinder Kumar Rana

IPC: H03K3/3562 ,  H01L27/11 ,  H03K3/012 ,  H03K19/017 ,  G11C11/41

Abstract: Various example embodiments herein disclose a flip-flop including a master latch comprising one of: a plurality of P-type metal-oxide-semiconductor (PMOS) and a plurality of N-type metal-oxide-semiconductor (NMOS). A slave latch includes one of: a plurality of PMOS and a plurality of NMOS. An inverted clock signal input is communicatively connected with the master latch and the slave latch. The master latch includes a single pre-charge node. The single pre-charge node sets up a data capture path in the flip flop. Data is stored in the master latch and the slave latch via the pre-charge node.