公开(公告)号：US10404240B2

公开(公告)日：2019-09-03

申请号：US15399146

申请日：2017-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Woo Kim ,  Min Su Kim ,  Ah Reum Kim ,  Chung Hee Kim

IPC: H03K3/356 ,  H03K3/3562 ,  H03K3/037

Abstract: Provided is a semiconductor device including low power retention flip-flop. The semiconductor device includes a first line to which a global power supply voltage is applied, a second line to which a local power supply voltage is applied, the second line being separated from the first line, a first operating circuit connected to the second line to use the local power supply voltage, a first power gating circuit determining whether the local power supply voltage is applied to the first operating circuit and a first retention flip-flop connected to the first line and the second line, wherein the first retention flip-flop comprises a first circuit including a master latch, a second circuit including a slave latch, and a first tri-state inverter connected between the master latch and the slave latch.

公开(公告)号：US10333498B2

公开(公告)日：2019-06-25

申请号：US15586011

申请日：2017-05-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Su Kim ,  Jong Woo Kim ,  Ji Kyum Kim

IPC: H03K3/356 ,  H03K3/012 ,  H03K3/037 ,  H03K3/3562 ,  H03K19/00

Abstract: An integrated circuit includes a plurality of positive edge-triggered master-slave flip-flop circuits sharing a clock signal. At least one of the positive edge-triggered master-slave flip-flop circuits includes; an input stage that provides a first output signal generated from an input signal in response to the clock signal and an inverted clock signal, a first inverting circuit that generates the inverted clock signal by delaying the clock signal, a transmission gate that receives a second output signal and generates a final output signal, and a second inverting circuit that receives the first output signal and generates the second output signal from the first output signal. The clock signal is applied to an NMOS transistor of the transmission gate and a PMOS transistor of the input stage, and the inverted clock signal is applied to a PMOS transistor of the transmission gate and an NMOS transistor of the input stage.

公开(公告)号：US20190089338A1

公开(公告)日：2019-03-21

申请号：US15969437

申请日：2018-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Su Kim ,  Dae Seong Lee

IPC: H03K3/3562

Abstract: A master-slave flip flop includes a master latch and a slave latch which are sequentially disposed on a substrate in a first direction. The master latch includes a first NMOS transistor and a first PMOS transistor each gated by a first clock signal. The first NMOS transistor and the first PMOS transistor share a first gate line extending in a second direction intersecting with the first direction. The slave latch includes a second NMOS transistor and a second PMOS transistor each gated by the first clock signal. The second NMOS transistor and the second NMOS transistor share a second gate line extending in the second direction. The first gate line and the second gate line are electrically connected to each other.

公开(公告)号：US11915782B2

公开(公告)日：2024-02-27

申请号：US17407585

申请日：2021-08-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chang Min Lee ,  Nam Hyung Kim ,  Dae Jeong Kim ,  Do Han Kim ,  Min Su Kim ,  Deok Ho Seo ,  Won Jae Shin ,  Yong Jun Yu ,  Il Gyu Jung ,  In Su Choi

IPC: G11C7/10 ,  G11C8/18 ,  G11C7/14

CPC classification number: G11C7/1063 ,  G11C7/109 ,  G11C7/1012 ,  G11C7/14 ,  G11C8/18

Abstract: An electronic device including a memory device with improved reliability is provided. The semiconductor device comprises a data pin configured to transmit a data signal, a command/address pin configured to transmit a command and an address, a command/address receiver connected to the command/address pin, and a computing unit connected to the command/address receiver, wherein the command/address receiver receives a first command and a first address from the outside through the command/address pin and generates a first instruction on the basis of the first command and the first address, and the computing unit receives the first instruction and performs computation based on the first instruction.

公开(公告)号：US10447248B2

公开(公告)日：2019-10-15

申请号：US16164329

申请日：2018-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Min Su Kim

IPC: H03K3/12 ,  H03K3/037 ,  H03K19/20 ,  H03K3/012

Abstract: A semiconductor circuit includes a first logic gate that receives inputs of a first input signal, a clock signal and a feedback signal and performs a first logical operation to output a first output signal. A second logic gate that receives inputs of the first output signal of the first logic gate, the clock signal, and an inverted output signal of the first input signal and performs a second logical operation to output the feedback signal.

公开(公告)号：US09876500B2

公开(公告)日：2018-01-23

申请号：US15499257

申请日：2017-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ah Reum Kim ,  Min Su Kim ,  Chung Hee Kim ,  Hyun Chul Hwang

IPC: H03K19/00 ,  H03K19/003 ,  H03K19/20

CPC classification number: H03K19/0013 ,  H03K3/012 ,  H03K3/356026 ,  H03K19/00315 ,  H03K19/20

Abstract: A semiconductor circuit includes a first circuit, a second circuit, a third circuit, and a fourth circuit. The first circuit determines a value of a first node based on a voltage level of a clock signal, and a voltage level of an enable signal or a voltage level of a scan enable signal. The second circuit determines a value of a second node based on the voltage levels of the first node and the clock signal. The third circuit determines a value of a third node based on a voltage level of the second node. The fourth circuit determines a value of a fourth node based on the voltage levels of the second node and the clock signal. The third circuit includes a first transistor and a second transistor connected in series with each other and gated to the voltage level of the second node to determine the value of the third node. The fourth circuit includes a third transistor that is gated to the voltage level of the clock signal to electrically connect the third node and the fourth node.

公开(公告)号：US20140176212A1

公开(公告)日：2014-06-26

申请号：US14028806

申请日：2013-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Min Su Kim

IPC: H03K3/02

CPC classification number: G01R31/318541 ,  H03K3/037

Abstract: A scan flip-flop may include a selector outputting a data signal or a scan input signal in response to a scan enable signal, and a flip-flop that latches an output signal of the selector or the data signal, based on a clock signal and a low voltage signal.

Abstract translation: 扫描触发器可以包括响应于扫描使能信号而输出数据信号或扫描输入信号的选择器和基于时钟信号锁存选择器或数据信号的输出信号的触发器，以及 低电压信号。

公开(公告)号：US11526194B2

公开(公告)日：2022-12-13

申请号：US17385182

申请日：2021-07-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun Chui Hwang ,  Min Su Kim

IPC: G06F1/08 ,  H03K5/156 ,  H03K3/037

Abstract: A semiconductor circuit may include a first flip-flop configured to output a first input data as a first output signal in response to an inverted input clock signal, a second flip-flop configured to output a second input data as a second output signal in response to an input clock signal, a glitch-free circuit configured to receive the inverted input clock signal, the input clock signal, the first output signal, and the second output signal, and to determine a voltage level of a node on the basis of the inverted input clock signal, the input clock signal, the first output signal, and the second output signal, and an inverter configured to output an output clock signal obtained by inverting the voltage level of the node determined by the glitch-free circuit. The glitch-free circuit does not include a transistor having a gate connected to the node.

公开(公告)号：US11277278B2

公开(公告)日：2022-03-15

申请号：US15778801

申请日：2016-11-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyun-Woo Ock ,  Sung Bin Im ,  Young Min Ko ,  Hyun Joong Kim ,  Hyun Jin Oh ,  Young Seon Kong ,  Min Su Kim ,  Seok Min Bae ,  Suk Tae Choi ,  Jung Mo Yeon ,  Lye Suk Lee

IPC: H04L12/28 ,  H04L29/06 ,  H04W12/06 ,  H04W12/08 ,  H04W4/70 ,  H04L69/08 ,  H04L67/125 ,  H04L69/18 ,  H04L67/12 ,  H04L67/56 ,  H04W12/71

Abstract: A smart home service which is capable of providing an environment in which calling a control command for a device is available via a user terminal protocol to control between the device and a user terminal based on different type of protocol and a control method for the same. The smart home service server connecting at least one device operated based on a first protocol to at least one user terminal operated based on a second protocol, includes an application programming interface (API) controller configured to allow a control command for the at least one device to be called via the second protocol of the at least one user terminal; a filter configured to convert the called control command according to the first protocol; and a control command transmitter configured to transmit the control command converted according to the first protocol, to the at least one device.

公开(公告)号：US11152922B2

公开(公告)日：2021-10-19

申请号：US16792343

申请日：2020-02-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： San Ha Kim ,  Taek Kyun Shin ,  Min Su Kim

IPC: H03K3/037 ,  G01R31/3183 ,  H03K19/20

Abstract: A semiconductor device includes a scan input circuit, a master latch, a slave latch, a first inverter, and a scan output circuit. The scan input circuit is configured to receive a scan input signal, a first data signal, and a scan enable signal and select any one of the first data signal and the scan input signal in response to the scan enable signal to output a first select signal. The master latch is configured to latch the first select signal and output a first output signal. The slave latch is configured to latch the first output signal and output a second output signal. The first inverter is configured to invert the second output signal. The scan output circuit is configured to receive a signal output from the slave latch and an external signal and output a first scan output signal.