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    INTEGRATED CIRCUIT MEMORY DEVICES HAVING EFFICIENT ROW HAMMER MANAGEMENT AND MEMORY SYSTEMS INCLUDING THE SAME
    22.
    发明公开
    INTEGRATED CIRCUIT MEMORY DEVICES HAVING EFFICIENT ROW HAMMER MANAGEMENT AND MEMORY SYSTEMS INCLUDING THE SAME 审中-公开

    公开(公告)号：US20240135980A1

    公开(公告)日：2024-04-25

    申请号：US18327335

    申请日：2023-05-31

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Myungkyu Lee ,  Eunae Lee ,  Sunghye Cho ,  Kyomin Sohn ,  Kijun Lee

    IPC: G11C11/406 ,  G06F12/02

    CPC classification number: G11C11/406 ,  G06F12/0223

    Abstract: A semiconductor memory device includes a memory cell array with a plurality of rows of memory cells therein, and a row hammer management (RHM) circuit including a hammer address queue. The RHM circuit is configured to: (i) receive first access row addresses from an external memory controller during a reference time interval, (ii) store a first row address randomly selected from the first access row addresses and second row addresses consecutively received from the memory controller after selecting the first row address, in the hammer address queue as candidate hammer addresses, and (iii) sequentially output the candidate hammer addresses as a hammer address. A refresh control circuit is provided to receive the hammer address and to perform a hammer refresh operation on one or more victim memory cell rows, which are physically adjacent to a memory cell row corresponding to the hammer address.

    Stacked memory device performing function-in-memory (FIM) operation and method of operating the same
    25.
    发明授权
    Stacked memory device performing function-in-memory (FIM) operation and method of operating the same 有权

    公开(公告)号：US11281397B2

    公开(公告)日：2022-03-22

    申请号：US17009992

    申请日：2020-09-02

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seongil O ,  Kyomin Sohn

    IPC: G06F3/06 ,  H01L25/065

    Abstract: A stacked memory device includes a plurality memory semiconductor dies, a plurality of through silicon vias, a function-in-memory (FIM) front-end circuit and a plurality of FIM back-end circuits. The buffer semiconductor die is configured to communicate with a host device. The memory semiconductor dies are stacked on the buffer semiconductor die, and include a plurality of memory banks. The through-silicon vias electrically connect the buffer semiconductor die and the memory semiconductor dies. The FIM front-end circuit receives a plurality of FIM instructions for a FIM operation from the host device, and stores the FIM instructions. The FIM operation includes data processing based on internal data read from the memory banks. The FIM back-end circuits are respectively included in the memory semiconductor dies. The FIM back-end circuits perform the FIM operation corresponding to the plurality of FIM instructions stored in the FIM front-end circuit under control of the FIM front-end circuit.

    Memory device for processing operation and method of operating the same
    26.
    发明授权
    Memory device for processing operation and method of operating the same 有权

    公开(公告)号：US11094371B2

    公开(公告)日：2021-08-17

    申请号：US16810344

    申请日：2020-03-05

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Seongil O ,  Shinhaeng Kang ,  Namsung Kim ,  Kyomin Sohn ,  Sukhan Lee

    IPC: G11C11/409 ,  G11C11/4096 ,  G06N3/063 ,  G06N3/04 ,  G06F13/16

    Abstract: A memory device includes a memory bank including at least one bank group, a processor in memory (PIM) circuit including a first processing element arranged to correspond to the bank group, which processes operations by using at least one of data provided by a host and data read from the bank group, a processing element input and output (PEIO) gating circuit configured to control electric connection between a bank local IO arranged to correspond to each bank of the bank group and a bank group IO arranged to correspond to the bank group, and a control logic configured to perform a control operation so that a memory operation for the memory bank is performed or operations are processed by the PIM circuit. When the operations are processed by the first processing element, the PEIO gating circuit blocks the electric connection between the bank local IO and the bank group IO.

    MEMORY DEVICES, MEMORY MODULES, AND OPERATING METHODS OF MEMORY DEVICES
    27.
    发明申请
    MEMORY DEVICES, MEMORY MODULES, AND OPERATING METHODS OF MEMORY DEVICES 有权

    公开(公告)号：US20210217461A1

    公开(公告)日：2021-07-15

    申请号：US16994796

    申请日：2020-08-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Sang-Hyuk Kwon ,  Nam Sung Kim ,  Kyomin Sohn ,  Seongil O ,  Haesuk Lee

    IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4096 ,  G11C11/4074

    Abstract: A memory device includes a memory cell array including a plurality of banks each including a plurality of memory cells connected to a plurality of word lines, and a row decoder block connected to the plurality of banks. In a first operation mode, the row decoder block receives a first row address and a first bank address together with an activation command and activates a word line selected by the first row address from among the plurality of word lines of a bank selected by the first bank address from among the plurality of banks. In a second operation mode, the row decoder block receives a second row address and a second bank address together with the activation command and activates a word line selected by the second row address from among the plurality of word lines of each of at least two banks of the plurality of banks.

    Memory device and refresh method thereof
    28.
    发明授权
    Memory device and refresh method thereof 有权

    公开(公告)号：US12236996B2

    公开(公告)日：2025-02-25

    申请号：US18197084

    申请日：2023-05-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Eun Ae Lee ,  Sunghye Cho ,  Kijun Lee ,  Kyomin Sohn ,  Myungkyu Lee

    IPC: G11C11/406

    Abstract: A memory device may include counters respectively corresponding to rows and each configured to count a number of accesses to a corresponding row, a refresh control circuit, a queue, and first flags respectively corresponding to the rows. The refresh control circuit may change a second flag set in a refresh period every refresh period, and determine whether to put an incoming row address into the queue based on a count value of a counter corresponding to a target row indicated by the incoming row address among the counters, a first flag value of a first flag corresponding to the target row among the first flags, and a second flag value of the second flag set in a current refresh period.

    Memory device
    30.
    发明授权
    Memory device 有权

    公开(公告)号：US12079482B2

    公开(公告)日：2024-09-03

    申请号：US17934691

    申请日：2022-09-23

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Shinhaeng Kang ,  Sukhan Lee ,  Kyomin Sohn

    IPC: G11C7/10 ,  G06F3/06 ,  G11C8/00

    CPC classification number: G06F3/0613 ,  G06F3/0629 ,  G06F3/0673 ,  G11C7/1006 ,  G11C8/00

    Abstract: A memory device includes a memory bank including a plurality of banks that comprise memory cells, and a PIM (processing in memory) circuit including a plurality of PIM blocks, each of the PIM blocks including an arithmetic logic unit (ALU) configured to perform an arithmetic operation using internal data acquired from at least one of the plurality of banks or an address generating unit. The plurality of PIM blocks include a first PIM block allocated to at least one first bank and a second PIM block allocated to at least one second bank. The address generating unit of the first PIM block is configured to generate a first internal row address for the at least one first bank, and the address generating unit of the second PIM block is configured to generate a second internal row address for the at least one second bank.

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