SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

    公开(公告)号:US20240103070A1

    公开(公告)日:2024-03-28

    申请号:US18230373

    申请日:2023-08-04

    CPC classification number: G01R31/2884 H01L22/32

    Abstract: Provided is a semiconductor device including a substrate including an element region and a scribe lane region defining the element region, and one or more test element groups arranged on the substrate and including one or more test elements for characteristic evaluation and one or more test pads for applying a test signal for testing the one or more test elements, wherein all of the one or more test pads are spaced apart from the element region in a horizontal direction.

    SEMICONDUCTOR CHIP AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME

    公开(公告)号:US20250062255A1

    公开(公告)日:2025-02-20

    申请号:US18670055

    申请日:2024-05-21

    Abstract: A semiconductor chip includes a semiconductor substrate including an active surface and an inactive surface opposite to the active surface, a wiring layer on the active surface, a front connection pad on the wiring layer, a lower protective insulating layer at least partially covering the wiring layer and including a lower opening that exposes at least a portion of the front connection pad, an upper protective insulating layer including an upper opening communicatively coupled to the lower opening on the lower protective insulating layer, a connection terminal coupled to the front connection pad through the lower opening and the upper opening, and an upper cover insulating layer between the connection terminal and the upper protective insulating layer. The upper protective insulating layer includes an organic material. The upper cover insulating layer includes an inorganic material.

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