公开(公告)号：US10355415B2

公开(公告)日：2019-07-16

申请号：US15916505

申请日：2018-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyung Joon Kim ,  Min-Seok Kim ,  Sigwan Kim ,  Jung-Woo Kim

IPC: H01R13/648 ,  H05K1/02 ,  H01R13/6471 ,  H01R13/6466 ,  H01R13/66 ,  H01R12/72

Abstract: An electronic device according to an example embodiment includes: a substrate; and a connector including a plurality of terminals disposed on a first area of the substrate, wherein the substrate includes: a first layer including signal lines connected to the plurality of terminals and a dielectric material disposed between the signal lines; a second layer disposed on the first layer, and including a first ground electrically connected with the connector and a second ground physically isolated from the first ground; a third conductive layer disposed on the second layer, and electrically connected with the second ground; and a fourth layer having a nonconductive material disposed on an area corresponding to the first area between the second layer and the third conductive layer.

公开(公告)号：US20180287302A1

公开(公告)日：2018-10-04

申请号：US15916505

申请日：2018-03-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyung Joon Kim ,  Min-Seok Kim ,  Sigwan Kim ,  Jung-Woo Kim

IPC: H01R13/6471 ,  H05K1/02 ,  H01R12/72 ,  H01R13/6466 ,  H01R13/66

CPC classification number: H01R13/6471 ,  H01R12/721 ,  H01R13/6466 ,  H01R13/6691 ,  H01R2201/16 ,  H05K1/0215 ,  H05K1/0218 ,  H05K1/0298 ,  H05K2201/0715 ,  H05K2201/095 ,  H05K2201/10189

Abstract: An electronic device according to an example embodiment includes: a substrate; and a connector including a plurality of terminals disposed on a first area of the substrate, wherein the substrate includes: a first layer including signal lines connected to the plurality of terminals and a dielectric material disposed between the signal lines; a second layer disposed on the first layer, and including a first ground electrically connected with the connector and a second ground physically isolated from the first ground; a third conductive layer disposed on the second layer, and electrically connected with the second ground; and a fourth layer having a nonconductive material disposed on an area corresponding to the first area between the second layer and the third conductive layer.

公开(公告)号：US12082410B2

公开(公告)日：2024-09-03

申请号：US17738516

申请日：2022-05-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yong-Hoon Son ,  Hyung Joon Kim ,  Hyun Jung Lee

IPC: H01L27/10 ,  H10B12/00 ,  H10B43/10

CPC classification number: H10B43/10 ,  H10B12/00 ,  H10B12/03 ,  H10B12/0335 ,  H10B12/05 ,  H10B12/31 ,  H10B12/482 ,  H10B12/488

Abstract: Disclosed are semiconductor memory devices and methods of fabricating the same. The semiconductor memory device comprises a first semiconductor pattern that is on a substrate and that includes a first end and a second end that face each other, a first conductive line that is adjacent to a lateral surface of the first semiconductor pattern between the first and second ends and that is perpendicular to a top surface of the substrate, a second conductive line that is in contact with the first end of the first semiconductor pattern, is spaced part from the first conductive line, and is parallel to the top surface of the substrate, and a data storage pattern in contact with the second end of the first semiconductor pattern. The first conductive line has a protrusion that protrudes adjacent to the lateral surface of the first semiconductor pattern.

公开(公告)号：US11864383B2

公开(公告)日：2024-01-02

申请号：US17495614

申请日：2021-10-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun Yeoung Choi ,  Hyung Joon Kim ,  Su Hyeong Lee ,  Jung Geun Jee

IPC: H10B41/30 ,  H10B43/27 ,  H01L29/10 ,  H01L29/16 ,  H01L21/768 ,  H01L21/02 ,  H01L21/28

CPC classification number: H10B43/27 ,  H01L21/0228 ,  H01L21/76802 ,  H01L21/76832 ,  H01L29/1033 ,  H01L29/16 ,  H01L29/40117

Abstract: A vertical-type memory device includes a plurality of gate electrodes stacked on a substrate; and a vertical channel structure penetrating through the plurality of gate electrodes in a first direction, perpendicular to an upper surface of the substrate. The vertical channel structure includes a channel extending in the first direction, a first filling film that partially fills an internal space of the channel, a first liner on at least a portion of an upper surface of the first filling film and an upper internal side wall of the channel extending beyond the first filling film away from the substrate. The first liner includes n-type impurities. The vertical channel structure includes a second filling film on at least a portion of the first liner, and a pad on the second filling film and in contact with the first liner.

公开(公告)号：US11164884B2

公开(公告)日：2021-11-02

申请号：US16359009

申请日：2019-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eun Yeoung Choi ,  Hyung Joon Kim ,  Su Hyeong Lee ,  Jung Geun Jee

IPC: H01L27/11582 ,  H01L29/10 ,  H01L29/16 ,  H01L21/768 ,  H01L21/02 ,  H01L21/28

Abstract: A vertical-type memory device includes a plurality of gate electrodes stacked on a substrate; and a vertical channel structure penetrating through the plurality of gate electrodes in a first direction, perpendicular to an upper surface of the substrate. The vertical channel structure includes a channel extending in the first direction, a first filling film that partially fills an internal space of the channel, a first liner on at least a portion of an upper surface of the first filling film and an upper internal side wall of the channel extending beyond the first filling film away from the substrate. The first liner includes n-type impurities. The vertical channel structure includes a second filling film on at least a portion of the first liner, and a pad on the second filling film and in contact with the first liner.

公开(公告)号：US10977491B2

公开(公告)日：2021-04-13

申请号：US15924742

申请日：2018-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyung Joon Kim ,  Heung Ki Lee ,  Byung Jun Son ,  Tae Hwa Hong ,  Hyung Suk Kim ,  Ji Yoon Park ,  Dae Kyu Shin ,  Je Han Yoon ,  Hoo Hyoung Lee ,  Sung Dae Cho

IPC: G06K9/00 ,  G06F3/0488 ,  G06K9/32 ,  G06F16/432 ,  G06Q30/02 ,  G06F3/0482 ,  G06K9/20 ,  G06Q30/06

Abstract: An electronic device includes a camera module, a display, and a processor. The processor is configured to display a preview image including one or more objects using the camera module, to display a first user interface corresponding to the one or more objects or a second user interface, in the display, to receive an input to select the first user interface or the second user interface, to obtain a first image in a first scheme using the camera module if the first user interface is selected, to obtain a second image using the camera module in a second scheme different from the first scheme if the second user interface is selected, and to provide information associated with the one or more objects using the first image and/or the second image, which is obtained based at least on the input.

公开(公告)号：US10468431B2

公开(公告)日：2019-11-05

申请号：US16027667

申请日：2018-07-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung Ho Kim ,  BiO Kim ,  Hyung Joon Kim ,  Young Seon Son ,  Su Jin Shin ,  Jae Young Ahn ,  Ju Mi Yun ,  HanMei Choi

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11568 ,  H01L21/28 ,  H01L29/792

Abstract: A semiconductor device includes gate electrodes vertically stacked on a substrate, and channel holes passing through the gate electrodes to extend perpendicularly to the substrate and including a gate dielectric layer and a channel area. The gate dielectric layer may be formed of a plurality of layers, and at least one layer among the plurality of layers may have different thicknesses in different locations.