公开(公告)号：US20230044856A1

公开(公告)日：2023-02-09

申请号：US17873242

申请日：2022-07-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejin PARK ,  Kiseok LEE ,  Hui-Jung KIM ,  Yoosang HWANG

IPC: H01L29/423 ,  H01L21/768 ,  H01L21/762 ,  H01L21/02 ,  G11C5/06

Abstract: A semiconductor memory device including a substrate including an active pattern that includes a first source/drain region and a second source/drain region; an insulating layer on the substrate; a line structure on the insulating layer and extending in a first direction to cross the active pattern, the line structure penetrating the insulating layer on the first source/drain region and including a bit line electrically connected to the first source/drain region; and a contact spaced apart from the line structure and electrically connected to the second source/drain region, wherein the bit line includes a first portion vertically overlapped with the first source/drain region; and a second portion vertically overlapped with the insulating layer, and wherein a lowermost level of a top surface of the first portion of the bit line is at a level lower than a lowermost level of a top surface of the second portion of the bit line.

公开(公告)号：US20230043936A1

公开(公告)日：2023-02-09

申请号：US17735292

申请日：2022-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Jin PARK ,  Gyul GO ,  Jun Soo KIM ,  Gyung Hyun YOON ,  Eui Jun CHA ,  Hui-Jung KIM ,  Yoo Sang HWANG

IPC: H01L27/108

Abstract: A semiconductor device and a method for fabricating the same is provided. The semiconductor device includes a lower semiconductor film, a buried insulating film, and an upper semiconductor film which are sequentially stacked; an element isolation film defining an active region inside the substrate and including a material having an etching selectivity with respect to silicon oxide; a first gate trench inside the upper semiconductor film; a first gate electrode filing a part of the first gate trench; a second gate trench inside the element isolation film; and a second gate electrode filling a part of the second gate trench, a bottom side of the element isolation film being inside the lower semiconductor film.

公开(公告)号：US20230019055A1

公开(公告)日：2023-01-19

申请号：US17954844

申请日：2022-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seok Han PARK ,  Yong Seok KIM ,  Hui-Jung KIM ,  Satoru YAMADA ,  Kyung Hwan LEE ,  Jae Ho HONG ,  Yoo Sang HWANG

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L49/02 ,  H01L29/78 ,  H01L29/45 ,  H01L29/786 ,  H01L29/06

Abstract: A semiconductor device is provided. The semiconductor device includes a first stacked structure including a plurality of first insulating patterns and a plurality of first semiconductor patterns alternately stacked on a substrate, the first stacked structure extending in a first direction parallel to an upper surface of the substrate, a first conductive pattern on one side surface of the first stacked structure, the first conductive pattern extending in a second direction crossing the upper surface of the substrate, and a first ferroelectric layer between the first stacked structure and the first conductive pattern, the first ferroelectric layer extending in the second direction, wherein each of the first semiconductor patterns includes a first impurity region, a first channel region and a second impurity region which are sequentially arranged along the first direction.

公开(公告)号：US20230005924A1

公开(公告)日：2023-01-05

申请号：US17667652

申请日：2022-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Taejin PARK ,  Hui-Jung KIM ,  Sangho LEE

IPC: H01L27/108

Abstract: A semiconductor memory device includes active regions including first impurity regions and second impurity regions, word lines on the active regions and extended in a first direction, bit lines on the word lines and extended in a second direction crossing the first direction, the bit lines being connected to the first impurity regions, first contact plugs between the bit lines, the first contact plugs being connected to the second impurity regions, landing pads on the first contact plugs, respectively, and gap-fill structures filling spaces between the landing pads, top surfaces of the gap-fill structures being higher than top surfaces of the landing pads.

公开(公告)号：US20200043941A1

公开(公告)日：2020-02-06

申请号：US16508839

申请日：2019-07-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hui-Jung KIM ,  Kiseok LEE ,  Keunnam KIM ,  Yoosang HWANG

IPC: H01L27/11578 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device may include a stack structure that includes a plurality of layers vertically stacked on a substrate, and a plurality of gate electrodes that vertically extend to penetrate the stack structure. Each of the plurality of layers may include a plurality of semiconductor patterns that extend in parallel along a first direction, a bit line that is electrically connected to the semiconductor patterns and extends in a second direction intersecting the first direction, a first air gap on the bit line, and a data storage element that is electrically connected to a corresponding one of the semiconductor patterns. The first air gap is interposed between the bit line of a first layer of the plurality of layers and the bit line of a second layer of the plurality of layers.

公开(公告)号：US20240365531A1

公开(公告)日：2024-10-31

申请号：US18768714

申请日：2024-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin PARK ,  Hui-Jung KIM ,  Sangho LEE

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/34 ,  H10B12/482

Abstract: A semiconductor memory device includes active regions including first impurity regions and second impurity regions, word lines on the active regions and extended in a first direction, bit lines on the word lines and extended in a second direction crossing the first direction, the bit lines being connected to the first impurity regions, first contact plugs between the bit lines, the first contact plugs being connected to the second impurity regions, landing pads on the first contact plugs, respectively, and gap-fill structures filling spaces between the landing pads, top surfaces of the gap-fill structures being higher than top surfaces of the landing pads.

公开(公告)号：US20240268101A1

公开(公告)日：2024-08-08

申请号：US18471900

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： SangJae PARK ,  Seung-Bo KO ,  Keunnam KIM ,  Jongmin KIM ,  Hui-Jung KIM ,  Taejin PARK ,  Chan-Sic YOON ,  Kiseok LEE ,  Myeong-Dong LEE ,  Hongjun LEE

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/05 ,  H10B12/34 ,  H10B12/485 ,  H10B12/488

Abstract: A semiconductor device includes first and second active patterns extending in a first direction and being adjacent to each other in a second direction, the first and second active patterns, each of which includes first and second edges spaced apart from each other in the first direction, a first storage node pad and a first storage node contact sequentially provided on the first edge of the first active pattern, a second storage node pad and a second storage node contact sequentially provided on the second edge of the second active pattern, and a fence pattern between the first and the second storage node contacts. Bottom and top surfaces of the first storage node contact are located at first and second levels, respectively. In a third direction, a width of the fence pattern at the first level is less than a width of the fence pattern at the second level.

公开(公告)号：US20230157003A1

公开(公告)日：2023-05-18

申请号：US17828298

申请日：2022-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Keunnam KIM ,  Yongseok KIM ,  Hui-Jung KIM ,  Min Hee CHO ,  Yoosang HWANG

IPC: H01L27/108

CPC classification number: H01L27/10805 ,  H01L27/10873 ,  H01L27/10897

Abstract: A semiconductor memory device including a stack structure including layer groups that are vertically stacked on a substrate and including a word line, a channel layer, and a data storage element that is electrically connected to the channel layer; and a vertically extending bit line on one side of the stack structure, wherein the word line of each of the layer groups extends in a first direction parallel to a top surface of the substrate, the layer groups include first and second layer groups that are sequentially stacked, the channel layer is below the word line of the first layer group, the channel layer is above the word line of the second layer group, and the bit line includes a first protrusion portion connected to the channel layer of the first layer group; and a second protrusion portion connected to the channel layer of the second layer group.

公开(公告)号：US20230084388A1

公开(公告)日：2023-03-16

申请号：US17730279

申请日：2022-04-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Keunnam KIM ,  Hui-Jung KIM ,  Min Hee CHO

IPC: H01L29/786 ,  H01L23/522 ,  H01L23/528

Abstract: A semiconductor device includes a substrate, a gate electrode on the substrate, a channel layer between the substrate and the gate electrode, the channel layer including an amorphous oxide semiconductor, and a width of the gate electrode being greater than a width of the channel layer, a first conductive electrode connected to a first side surface of the channel layer, and a second conductive electrode connected to a second side surface of the channel layer.

公开(公告)号：US20230055147A1

公开(公告)日：2023-02-23

申请号：US17741701

申请日：2022-05-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Keunnam KIM ,  Hui-Jung KIM ,  Wonsok LEE ,  Min Hee CHO

IPC: H01L27/108 ,  H01L29/786 ,  H01L29/66

Abstract: A semiconductor memory device is disclosed. The semiconductor memory device may include a bit line extending in a first direction, a word line extending in a second direction perpendicular to the first direction, a channel pattern between the bit line and the word line, the channel pattern including a horizontal channel portion, which is connected to the bit line, and a vertical channel portion, which is extended from the horizontal channel portion in a third direction perpendicular to the first and second directions, and a gate insulating pattern between the word line and the channel pattern. The horizontal channel portion of the channel pattern may be disposed parallel to a fourth direction that is inclined to the first and second directions.