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    SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHODS OF OPERATING MEMORY SYSTEMS
    21.
    发明申请
    SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS INCLUDING THE SAME AND METHODS OF OPERATING MEMORY SYSTEMS 有权

    公开(公告)号：US20220121518A1

    公开(公告)日：2022-04-21

    申请号：US17562505

    申请日：2021-12-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hoi-Ju Chung ,  Sang-Uhn Cha ,  Ho-Young Song ,  Hyun-Joong Kim

    IPC: G06F11/10 ,  G11C29/52 ,  G06F3/06

    Abstract: A semiconductor memory device includes a memory cell array, an error correction circuit, an error log register and a control logic circuit. The memory cell array includes a plurality of memory bank arrays and each of the memory bank arrays includes a plurality of pages. The control logic circuit is configured to control the error correction circuit to perform an ECC decoding sequentially on some of the pages designated at least one access address for detecting at least one bit error, in response to a first command received from a memory controller. The control logic circuit performs an error logging operation to write page error information into the error log register and the page error information includes a number of error occurrence on each of the some pages determined from the detecting.

    Semiconductor memory devices and methods of operating the same
    24.
    发明授权
    Semiconductor memory devices and methods of operating the same 有权

    公开(公告)号：US10156995B2

    公开(公告)日：2018-12-18

    申请号：US15398409

    申请日：2017-01-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Sang-Uhn Cha ,  Hoi-Ju Chung ,  Ye-Sin Ryu ,  Seong-Jin Cho

    IPC: G06F3/06 ,  H03M13/15 ,  G11C29/52 ,  G11C11/16 ,  G06F11/10 ,  H03M13/00 ,  G11C29/00 ,  G11C29/04

    Abstract: A semiconductor memory device includes a memory cell array, a control logic circuit, and an error correction circuit. The control logic circuit generates control signals by decoding a command. The control logic circuit, in a write mode of the semiconductor memory device, controls the error correction circuit to read a first unit of data from a selected sub-page and to generate a first parity data based on one of the first sub unit of data and the second sub unit of data and a main data to be written into the sub-page while generating syndrome data by performing an error correction code decoding on the first unit of data. The error correction circuit, when a first sub unit of data includes at least one error bit, selectively modifies the first parity data based on a data mask signal associated with the main data.

    Nonvolatile memory device having read circuits for performing Read-While-Write (RWW) operation and Read-Modify-Write (RMW) operation
    27.
    发明授权
    Nonvolatile memory device having read circuits for performing Read-While-Write (RWW) operation and Read-Modify-Write (RMW) operation 有权
    具有用于执行读写（RWW）操作和读取 - 修改 - 写入（RMW）操作的读取电路的非易失性存储器件

    公开(公告)号：US09135994B2

    公开(公告)日：2015-09-15

    申请号：US14171873

    申请日：2014-02-04

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hyo-Jin Kwon ,  Hoi-Ju Chung ,  Chae-Hoon Kim ,  Yong-Jin Kwon ,  Eun-Hye Park ,  Yong-Jun Lee

    IPC: G11C7/22 ,  G11C13/00

    CPC classification number: G11C13/004 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0061 ,  G11C2213/72

    Abstract: A nonvolatile memory device includes a memory array having multiple nonvolatile memory cells, a first read circuit and a second read circuit. The first read circuit is configured to read first data from the memory array during a first read operation and to provide one or more protection signals indicating a victim period during the first read operation. The second read circuit is configured to read second data from the memory array during a second read operation and to provide one or more check signals indicating an aggressor period during the second read operation.

    Abstract translation: 非易失性存储器件包括具有多个非易失性存储单元的存储器阵列，第一读取电路和第二读取电路。 第一读取电路被配置为在第一读取操作期间从存储器阵列读取第一数据，并且在第一读取操作期间提供指示受害时段的一个或多个保护信号。 第二读取电路被配置为在第二读取操作期间从存储器阵列读取第二数据，并且在第二读取操作期间提供指示侵略者周期的一个或多个检查信号。

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