公开(公告)号：US20190214391A1

公开(公告)日：2019-07-11

申请号：US16053315

申请日：2018-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-Sic Yoon ,  Dongoh Kim ,  Kiseok Lee ,  Sunghak Cho ,  Jemin Park

IPC: H01L27/108 ,  H01L21/762

Abstract: A semiconductor device includes a substrate that includes a cell region and a peripheral circuit region, a cell insulating pattern disposed in the cell region of the substrate that defines a cell active region, and a peripheral insulating pattern disposed in the peripheral circuit region of the substrate that defines a peripheral active region. The peripheral insulating pattern includes a first peripheral insulating pattern having a first width and a second peripheral insulating pattern having a second width greater than the first width. A topmost surface of at least one of the first peripheral insulating pattern and the second peripheral insulating pattern is positioned higher than a topmost surface of the cell insulating pattern.

公开(公告)号：US12218212B2

公开(公告)日：2025-02-04

申请号：US18496336

申请日：2023-10-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doosan Back ,  Dongoh Kim ,  Gyuhyun Kil ,  Jung-Hoon Han

IPC: H01L29/423 ,  H01L29/417 ,  H01L29/51

Abstract: A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.

公开(公告)号：US12051880B2

公开(公告)日：2024-07-30

申请号：US17194901

申请日：2021-03-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongoh Kim ,  Jongpil Seo ,  Dongchan Lee ,  Youngchan Lee ,  Jiseok Jung ,  Minwoo Cha ,  Yoongoo Han

IPC: H01R4/20 ,  H01R13/52 ,  H02G3/22 ,  H02G15/013

CPC classification number: H01R4/20 ,  H01R13/5216 ,  H02G3/22 ,  H02G15/013

Abstract: A display apparatus including a housing, a display module arranged inside the housing to display an image, a printed circuit board (PCB) connected to a plurality of cables provided to be electrically connected to the display module, a board case having a receiving space formed within the board case, the receiving space accommodating the PCB, and a cable clamp arranged on the board case to close a side of the receiving space, wherein the cable clamp includes a body, a first cut which is cut from a side of the body, a plurality of second cuts branched from an end of the first cut, and a plurality of through holes formed at one ends of the plurality of second cuts and passing through the body, each through hole having one of the plurality of cables inserted to and coupled with the through hole.

公开(公告)号：US11917815B2

公开(公告)日：2024-02-27

申请号：US18123736

申请日：2023-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyosub Kim ,  Keunnam Kim ,  Dongoh Kim ,  Bongsoo Kim ,  Euna Kim ,  Chansic Yoon ,  Kiseok Lee ,  Hyeonok Jung ,  Sunghee Han ,  Yoosang Hwang

IPC: H10B12/00 ,  H01L27/108 ,  H01L23/528

CPC classification number: H10B12/315 ,  H01L23/5283 ,  H10B12/053 ,  H10B12/34 ,  H10B12/482 ,  H10B12/485 ,  H10B12/488

Abstract: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.

公开(公告)号：US20230232618A1

公开(公告)日：2023-07-20

申请号：US18123736

申请日：2023-03-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyosub Kim ,  Keunnam Kim ,  Dongoh Kim ,  Bongsoo Kim ,  Euna Kim ,  Chansic Yoon ,  Kiseok Lee ,  Hyeonok Jung ,  Sunghee Han ,  Yoosang Hwang

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/34 ,  H10B12/053 ,  H10B12/315 ,  H10B12/482

Abstract: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.

公开(公告)号：US11545554B2

公开(公告)日：2023-01-03

申请号：US17406162

申请日：2021-08-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doosan Back ,  Dongoh Kim ,  Gyuhyun Kil ,  Jung-Hoon Han

IPC: H01L29/423 ,  H01L29/417 ,  H01L29/51

Abstract: A semiconductor device includes a gate stack including a gate insulating layer and a gate electrode on the gate insulating layer. The gate insulating layer includes a first dielectric layer and a second dielectric layer on the first dielectric layer, and a dielectric constant of the second dielectric layer is greater than a dielectric constant of the first dielectric layer. The semiconductor device also includes a first spacer on a side surface of the gate stack, and a second spacer on the first spacer, wherein the second spacer includes a protruding portion extending from a level lower than a lower surface of the first spacer towards the first dielectric layer, and a dielectric constant of the second spacer is greater than the dielectric constant of the first dielectric layer and less than a dielectric constant of the first spacer.

公开(公告)号：US11201156B2

公开(公告)日：2021-12-14

申请号：US16934874

申请日：2020-07-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chan-Sic Yoon ,  Dongoh Kim ,  Kiseok Lee ,  Sunghak Cho ,  Jemin Park

IPC: H01L27/108 ,  H01L21/762 ,  H01L21/311

Abstract: A semiconductor device includes a substrate that includes a cell region and a peripheral circuit region, a cell insulating pattern disposed in the cell region of the substrate that defines a cell active region, and a peripheral insulating pattern disposed in the peripheral circuit region of the substrate that defines a peripheral active region. The peripheral insulating pattern includes a first peripheral insulating pattern having a first width and a second peripheral insulating pattern having a second width greater than the first width. A topmost surface of at least one of the first peripheral insulating pattern and the second peripheral insulating pattern is positioned higher than a topmost surface of the cell insulating pattern.

公开(公告)号：US20210066305A1

公开(公告)日：2021-03-04

申请号：US16896470

申请日：2020-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyosub Kim ,  Keunnam Kim ,  Dongoh Kim ,  Bongsoo Kim ,  Euna Kim ,  Chansic Yoon ,  Kiseok Lee ,  Hyeonok Jung ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L23/528

Abstract: A semiconductor device includes: an active region defined by a device isolation layer formed in a substrate; a word line configured to cross the active region, the word line extending in a first direction and being formed in the substrate; a bit line extending in a second direction perpendicular to the first direction on the word line; a first contact connecting the bit line to the active region; a first mask for forming the active region, the first mask being formed on the active region; and a second mask of which a height of a top surface thereof is greater than a height of a top surface of the active region, the second mask covering the word line, wherein the active region has a bar shape that extends to form an acute angle with respect to the first direction.

公开(公告)号：US10332890B2

公开(公告)日：2019-06-25

申请号：US15653198

申请日：2017-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok Lee ,  Chan-Sic Yoon ,  Augustin Hong ,  Keunnam Kim ,  Dongoh Kim ,  Bong-Soo Kim ,  Jemin Park ,  Hoin Lee ,  Sungho Jang ,  Kiwook Jung ,  Yoosang Hwang

IPC: H01L27/108 ,  H01L27/24 ,  H01L27/22

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.