公开(公告)号：US20220374498A1

公开(公告)日：2022-11-24

申请号：US17672060

申请日：2022-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changwook JEONG ,  Dongjin LEE ,  Kijung SHIN

IPC: G06F17/16

Abstract: A tensor data processing method is provided. The method comprises receiving an input tensor including at least one of an outlier and a missing value, the input tensor being input during a time interval between a first time point and a second time point, factorizing the input tensor into a low rank tensor to extract a temporal factor matrix, calculating trend and periodic pattern from the extracted temporal factor matrix, detecting the outlier which is out of the calculated trend and periodic pattern, updating the temporal factor matrix except the detected outlier, combining the updated temporal factor matrix and a non-temporal factor matrix of the input tensor to calculate the real tensor and recovering the input tensor by setting data corresponding to a position of the outlier or a position of the missing value of the input tensor from the data of the real tensor as an estimated value.

公开(公告)号：US20190265873A1

公开(公告)日：2019-08-29

申请号：US16343519

申请日：2017-10-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hark-Joon KIM ,  Taeyeon WON ,  Dongjin LEE ,  Youn Ju JIN ,  Jinah KONG ,  Yangjic LEE ,  Hanui YUN ,  Saerom HWANG

IPC: G06F3/0484 ,  G06F3/0482 ,  G06Q30/02

Abstract: Various embodiments of the present invention relate to a device and a method for setting an area for an interaction of reactive content in an electronic device, wherein an electronic device operating method can comprise the steps of: displaying an image acquired from an external electronic device electrically connected to the electronic device; correcting the image into a top view form; displaying a guide interface of a lattice pattern form such that the image corrected into a top view form is overlapped therewith; selecting at least a partial area of the guide interface; applying spatial coordinates for the at least partial area so as to set an area for an interaction in a sensor of the external electronic device; copying the selected at least partial area and attaching the same to an adjacent other area; and mapping content to the area for an interaction. Other embodiments are possible.

公开(公告)号：US20190198626A1

公开(公告)日：2019-06-27

申请号：US16288910

申请日：2019-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin LEE ,  Junsoo KIM ,  Moonyoung JEONG ,  Satoru YAMADA ,  Dongsoo WOO ,  Jiyoung KIM

IPC: H01L29/40 ,  H01L27/108 ,  H01L29/66 ,  B82Y10/00 ,  H01L27/12 ,  H01L29/423 ,  H01L29/786 ,  H01L29/775 ,  H01L21/84

CPC classification number: H01L29/402 ,  B82Y10/00 ,  H01L21/84 ,  H01L27/088 ,  H01L27/10876 ,  H01L27/1203 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78639 ,  H01L29/78696

Abstract: A semiconductor device may include a device isolation region configured to define an active region in a substrate, an active gate structure disposed in the active region, and a field gate structure disposed in the device isolation region. The field gate structure may include a gate conductive layer. The active gate structure may include an upper active gate structure including a gate conductive layer and a lower active gate structure formed under the upper active gate structure and vertically spaced apart from the upper active gate structure. The lower active gate structure may include a gate conductive layer. A top surface of the gate conductive layer of the field gate structure is located at a lower level than a bottom surface of the gate conductive layer of the upper active gate structure.

公开(公告)号：US20250126799A1

公开(公告)日：2025-04-17

申请号：US18673528

申请日：2024-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kang-Oh YUN ,  Yunjo LEE ,  Dongjin LEE ,  Jaeduk LEE

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A semiconductor device may include a substrate containing first to third doping regions, first and second gate structures between the first and second doping regions, and a gate separation layer between the first and second gate structures. Each of the first and second gate structures may include a first gate dielectric layer, a first gate conductive layer on the first gate dielectric layer, and a second gate conductive layer between the gate separation layer and the first gate conductive layer. The gate separation layer may include a first sidewall in contact with the first gate structure and a second sidewall in contact with the second gate structure. A top surface of the gate separation layer may be at a same level as a top surface of the second gate conductive layer.

公开(公告)号：US20250022764A1

公开(公告)日：2025-01-16

申请号：US18412770

申请日：2024-01-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minjung KIM ,  Solji SONG ,  Jiseok YEO ,  Hyojun YOON ,  Dongjin LEE ,  Yoonseok CHOI

IPC: H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package is provided. The semiconductor package includes a package substrate including bonding pads on a upper surface thereof and external connectors on a lower surface thereof, a first chip structure connected to the package substrate with a bonding wire and disposed on the package substrate, a second chip structure disposed on the package substrate and disposed next to the first chip structure, and a mold layer covering the package substrate, the first chip structure, and the second chip structure, wherein the first chip structure includes a plurality of semiconductor dies that are sequentially stacked, the second chip structure includes a second semiconductor substrate, an oxide layer on the second semiconductor substrate, and an adhesion enhancer layer disposed on the oxide layer and in contact with the mold layer, heights of the first chip structure and the second chip structure are the same.

公开(公告)号：US20240179899A1

公开(公告)日：2024-05-30

申请号：US18514158

申请日：2023-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseon KIM ,  Nakjin SON ,  Dongjin LEE ,  Junhee LIM ,  Seongsu KIM ,  Hanmin CHO ,  Chiwoong HAM

IPC: H10B41/41 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

CPC classification number: H10B41/41 ,  G11C16/0483 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40

Abstract: A NAND flash device may include a peripheral circuit including a transistor, a substrate, and a device isolation region defining an active region of the substrate. The transistor may include a first gate structure on the active region. The transistor may include source and drain regions extending in a first direction in the active region on both sides of the first gate structure, which may include a first lightly-doped source and drain region adjacent to the first gate structure and a second lightly-doped source and drain region integrally connected thereto. The second lightly-doped source and drain region may be arranged farther from the first gate structure than the first lightly-doped source and drain region. The second lightly-doped source and drain region may have a smaller width in the second direction than a width of the first lightly-doped source and drain region in the second direction.

公开(公告)号：US20230422058A1

公开(公告)日：2023-12-28

申请号：US18462065

申请日：2023-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaesik YOON ,  Dongjin LEE ,  Changsung LEE ,  Junyoung CHO ,  Jungah CHOI

IPC: H04W24/02 ,  H04W24/08 ,  H04W24/04 ,  H04L5/00 ,  H04L41/0816 ,  H04W16/18

CPC classification number: H04W24/02 ,  H04W24/08 ,  H04W24/04 ,  H04L5/006 ,  H04L41/0816 ,  H04W16/18

Abstract: The present invention relates to method and device for sharing state related information among a plurality of electronic devices and, more particularly, to method and device for predicting the state of a device on the basis of information shared among a plurality of electronic devices. In order to attain the purpose, a method for sharing state related information of a device, according to an embodiment of the present invention, comprises the steps of: generating a state model of a device on the basis of state related data; selecting one or more parameters for determining the state of the device on the basis of the generated state model; and transmitting the one or more selected parameters to at least one other device.

公开(公告)号：US20230168712A1

公开(公告)日：2023-06-01

申请号：US17894702

申请日：2022-08-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yeonho KIM ,  Beomhan KIM ,  Dongjin LEE

IPC: G06F1/16 ,  G06F1/20

CPC classification number: G06F1/1607 ,  G06F1/20

Abstract: A display apparatus includes: a display panel; a rear chassis covering a rear surface of the display panel; a support frame coupled to the rear chassis; a panel holder provided on the rear surface of the display panel to face the support frame, the panel holder being configured to be coupled to the support frame to attach the display panel to the rear chassis; and a wire configured to: couple the panel holder to the support frame based on the wire being coupled to the panel holder and the support frame, and release the coupling between the panel holder and the support frame based on the wire being separated from the panel holder and the support frame.

公开(公告)号：US20220406808A1

公开(公告)日：2022-12-22

申请号：US17724002

申请日：2022-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjin LEE ,  Junhee LIM ,  Hakseon KIM ,  Nakjin SON ,  Jeongeun KIM ,  Juseong MIN ,  Changheon LEE

IPC: H01L27/11573 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582

Abstract: A semiconductor device includes a lower level layer including a peripheral circuit; and an upper level layer provided on the lower level layer, the upper level layer including a vertically-extended memory cell string, wherein the lower level layer includes a first substrate; a device isolation layer defining a first active region of the first substrate; and a first gate structure including a first gate insulating pattern, a first conductive pattern, a first metal pattern, and a first capping pattern, which are sequentially stacked on the first active region, wherein the first conductive pattern comprises a doped semiconductor material, and the device isolation layer covers a first side surface of the first conductive pattern, and the first metal pattern includes a first body portion on the first conductive pattern.

公开(公告)号：US20210199233A1

公开(公告)日：2021-07-01

申请号：US17132197

申请日：2020-12-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heungsung JUNG ,  Honggyun KIM ,  Byungnam LEE ,  Yonghwan PARK ,  Dongjin LEE ,  Bongsup LIM

IPC: F16M11/04 ,  F16M11/22

Abstract: Disclosed is a display apparatus including a display including a stand mounting part, a stand to which the stand mounting part is coupleable to mount the display on the stand, and a protection member comprising a portion that includes a support protection member and is detachably coupleable along an edge of the display so that, when the portion is coupled along the edge of the display, the support protection member covers a lower end portion of the display, and a mounting part protection member that is detachably coupleable along the edge of the display so that, when the mounting part protection member is coupled along the edge of the display, the mounting part protection member covers a portion of the display along which the stand is mountable, wherein the mounting part protection member is separately detachable from along the edge of the display while the portion that includes the support protection member remains coupled along the edge of the display with the support protection member covering the lower end portion of the display, to thereby uncover the portion of the display along which the stand is mountable.