公开(公告)号：US11942446B2

公开(公告)日：2024-03-26

申请号：US17165429

申请日：2021-02-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoeun Kim ,  Sunkyoung Seo ,  Seunghoon Yeon ,  Chajea Jo

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L24/14 ,  H01L23/3157 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/0657 ,  H01L2224/14181

Abstract: A semiconductor package includes at least one second semiconductor chip stacked on a first semiconductor chip. An underfill layer is interposed between the first semiconductor chip and the at least one second semiconductor chip. The first semiconductor chip includes a first substrate, a first passivation layer disposed on the first substrate. The first passivation layer includes a first recess region. A first pad covers a bottom surface and sidewalls of the first recess region. The at least one second semiconductor chip includes a second substrate, a second passivation layer disposed adjacent to the first substrate, a conductive bump protruding outside the second passivation layer towards the first semiconductor chip and an inter-metal compound pattern disposed in direct contact with both the conductive bump and the first pad. The underfill layer is in direct contact with both the conductive bump and the inter-metal compound pattern.

公开(公告)号：US11776941B2

公开(公告)日：2023-10-03

申请号：US17357378

申请日：2021-06-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghoe Cho ,  Sunkyoung Seo ,  Chajea Jo

IPC: H01L23/498 ,  H01L25/16 ,  H01L23/14 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L25/167 ,  H01L23/147 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/5383 ,  H01L24/16 ,  H01L2224/16227

Abstract: A semiconductor package includes a package substrate, a connection substrate on the package substrate, a first image sensor chip on the connection substrate, a second image sensor chip on the connection substrate, the second image sensor chip being horizontally spaced apart from the first image sensor chip, and a memory chip disposed on the package substrate and electrically connected to the first image sensor chip through the connection substrate. A distance between the first image sensor chip and the second image sensor chip is less than a thickness of the first image sensor chip.

公开(公告)号：US20230163090A1

公开(公告)日：2023-05-25

申请号：US18048606

申请日：2022-10-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chajea Jo ,  Inhyo Hwang

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A memory device is provided. The memory device includes a first structure and a second structure stacked on the first structure in a vertical direction. The first structure includes a first substrate, peripheral circuitry, an auxiliary memory cell array, a first insulating layer, and a plurality of first bonding pads. The second structure includes a second substrate, a main memory cell array, a second insulating layer, and a plurality of second bonding pads. The plurality of first bonding pads are in contact with the plurality of second bonding pads, respectively.

公开(公告)号：US20220216186A1

公开(公告)日：2022-07-07

申请号：US17705872

申请日：2022-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanguk Han ,  Chajea Jo ,  Hyoeun Kim ,  Sunkyoung Seo

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

Abstract: A package-on-package type package includes a lower semiconductor package and an upper semiconductor package. The lower semiconductor package includes a first semiconductor device including a through electrode, a second semiconductor device disposed on the first semiconductor device and including a second through electrode electrically connected to the first through electrode, a first molding member covering a sidewall of at least one of the first semiconductor device and the second semiconductor device, a second molding member covering a sidewall of the first molding member, and an upper redistribution layer disposed on the second semiconductor device and electrically connected to the second through electrode.

公开(公告)号：US11158603B2

公开(公告)日：2021-10-26

申请号：US16298476

申请日：2019-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyoeun Kim ,  Ji Hwang Kim ,  Jisun Yang ,  Seunghoon Yeon ,  Chajea Jo ,  Sang-Uk Han

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/538

Abstract: A semiconductor package includes a first semiconductor chip, a second semiconductor chip on the first semiconductor chip, a first semiconductor structure and a second semiconductor structure that are on the first semiconductor chip and spaced apart from each other across the second semiconductor chip, and a resin-containing member between the second semiconductor chip and the first semiconductor structure and between the second semiconductor chip and the second semiconductor structure. The semiconductor package may be fabricated at a wafer level.

公开(公告)号：US10978431B2

公开(公告)日：2021-04-13

申请号：US16287249

申请日：2019-02-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongbo Shim ,  Ji Hwang Kim ,  Chajea Jo ,  Sang-Uk Han

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00

Abstract: A semiconductor package includes a lower substrate, a connection substrate coupled to the lower substrate, the connection substrate having a lateral portion surrounding a cavity, and a first conductive pattern on a top surface of the lateral portion, a lower semiconductor chip on the lower substrate, the lower semiconductor chip being in the cavity of the connection substrate, and the lower semiconductor chip including a second conductive pattern on a top surface of the lower semiconductor chip, a bonding member connecting the first conductive pattern and the second conductive pattern to each other, and a top package on the first conductive pattern and the second conductive pattern.

公开(公告)号：US10361170B2

公开(公告)日：2019-07-23

申请号：US15837187

申请日：2017-12-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sungeun Pyo ,  Jongbo Shim ,  Ji Hwang Kim ,  Chajea Jo ,  Sang-Uk Han

IPC: H01L23/495 ,  H01L25/065 ,  H01L23/538 ,  H01L21/48 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor package including a first substrate including first upper pads, the first upper pads on a top surface of the first substrate, a second substrate including second upper pads, the second upper pads on a top surface of the second substrate, a pitch of the second upper pads being less than a pitch of the first upper pads, and a first semiconductor chip on and electrically connected to both (i) at least one of the first upper pads and (ii) at least one of the second upper pads may be provided.

公开(公告)号：US11990452B2

公开(公告)日：2024-05-21

申请号：US18120587

申请日：2023-03-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Namhoon Kim ,  Chajea Jo ,  Ohguk Kwon ,  Hyoeun Kim ,  Seunghoon Yeon

IPC: H01L25/065 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L24/02 ,  H01L25/0652 ,  H01L2224/02372 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/18161

Abstract: A semiconductor package includes a first semiconductor chip comprising a semiconductor substrate and a redistribution pattern on a top surface of the semiconductor substrate, the redistribution pattern having a hole exposing an inner sidewall of the redistribution pattern, a second semiconductor chip on a top surface of the first semiconductor chip, and a bump structure disposed between the first semiconductor chip and the second semiconductor chip. The bump structure is disposed in the hole and is in contact with the inner sidewall of the redistribution pattern.

公开(公告)号：US11887913B2

公开(公告)日：2024-01-30

申请号：US18066487

申请日：2022-12-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chajea Jo ,  Ohguk Kwon ,  Namhoon Kim ,  Hyoeun Kim ,  Seunghoon Yeon

IPC: H01L23/48 ,  H01L25/065 ,  H01L21/768 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L23/562 ,  H01L24/05 ,  H01L24/13 ,  H01L25/0652 ,  H01L2224/05008 ,  H01L2224/05025 ,  H01L2224/13026 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2924/351

Abstract: An integrated circuit device includes a semiconductor substrate, first through-silicon-via (TSV) structures penetrating a first region of the semiconductor substrate and spaced apart from each other by a first pitch, a first individual device between the first TSV structures and spaced apart from the first TSV structures by a distance that is greater than a first keep-off distance, and second TSV structures penetrating a second region of the semiconductor substrate and spaced apart from each other by a second pitch that is less than the first pitch. The second region of the semiconductor device does not include an individual device that is homogeneous with the first individual device and between the second TSV structures.

公开(公告)号：US20240006272A1

公开(公告)日：2024-01-04

申请号：US18296056

申请日：2023-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Juhyeon Kim ,  Ilhwan Kim ,  Sunkyoung Seo ,  Chajea Jo

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L23/498 ,  H01L23/31 ,  H01L21/56 ,  H01L23/532

CPC classification number: H01L23/481 ,  H01L25/0657 ,  H01L24/16 ,  H01L23/49822 ,  H01L23/3128 ,  H01L21/565 ,  H01L24/05 ,  H01L24/32 ,  H01L24/73 ,  H01L23/5329 ,  H01L23/49838 ,  H01L2225/06513 ,  H01L2224/16235 ,  H01L2224/0557 ,  H01L2224/73203 ,  H01L2224/32225

Abstract: A semiconductor package includes: a first semiconductor chip including first pads; a second semiconductor chip below the first semiconductor chip, the second semiconductor chip including a substrate including a front surface and an opposing rear surface, second pads on the front surface and in contact with the first pads, and through-electrodes electrically connected to the second pads and including protruding portions protruding from the rear surface of the substrate; through-via structures disposed around the second semiconductor chip and in contact with the first pads; a first dielectric layer extending along the rear surface of the substrate and side surfaces of the protruding portions of the through-electrodes; a second dielectric layer below the first dielectric layer and in a space between the protruding portions of the through-electrodes and between the through-via structures; and bump structures below the second dielectric layer and electrically connected to the through-electrodes and the through-via structures.