公开(公告)号：US09502445B2

公开(公告)日：2016-11-22

申请号：US14809372

申请日：2015-07-27

Applicant: Samsung Display Co., Ltd.

Inventor： Je-Hun Lee ,  Ki-Won Kim ,  Do-Hyun Kim ,  Woo-Geun Lee ,  Kap-Soo Yoon

IPC: H01L29/10 ,  H01L27/12 ,  H01L29/51 ,  H01L29/786 ,  H01L29/45 ,  H01L23/532 ,  H01L29/49 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L27/1225 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02554 ,  H01L21/02565 ,  H01L23/53238 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1262 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A TFT array substrate includes a semiconductive oxide layer disposed on an insulating substrate and including a channel portion, a gate electrode overlapping the semiconductive oxide layer, a gate insulating layer interposed between the semiconductive oxide layer and the gate electrode, and a passivation layer disposed on the semiconductive oxide layer and the gate electrode. At least one of the gate insulating layer and the passivation layer includes an oxynitride layer, and the oxynitride layer has a higher concentration of oxygen than that of nitrogen in a location of the oxynitride layer closer to the semiconductive oxide layer.

公开(公告)号：US09171864B2

公开(公告)日：2015-10-27

申请号：US14249199

申请日：2014-04-09

Applicant: Samsung Display Co., LTD.

Inventor： Xinxing Li ,  Do-Hyun Kim ,  Chan-Woo Yang ,  Jeong-Ju Park ,  Jun-Hyun Park ,  Xun Zhu

IPC: H01L21/84 ,  H01L27/12

CPC classification number: H01L27/1225 ,  H01L27/1259 ,  H01L27/1288

Abstract: A display substrate includes a gate metal pattern including a gate line disposed on a base substrate and a gate electrode electrically connected with the gate line, an active pattern entirely overlapped with the gate metal pattern and comprising an oxide semiconductor and a data metal pattern disposed on the active pattern and including a data line, a source electrode electrically connected with the gate line and a drain electrode spaced apart from the source electrode. The active pattern has an overlapped region in which the active pattern is overlapped with the source electrode and the drain electrode and an exposed region in which the active pattern is not overlapped with the source electrode and the drain electrode. The thickness of the overlapping region and a thickness of the exposing region are same.

Abstract translation: 显示基板包括栅极金属图案，其包括设置在基底基板上的栅极线和与栅极线电连接的栅电极，与栅极金属图案完全重叠的有源图案，并且包括氧化物半导体和数据金属图案， 所述有源图案包括数据线，与所述栅极线电连接的源电极和与所述源电极间隔开的漏电极。 有源图案具有重叠区域，其中有源图案与源电极和漏电极重叠，并且有源图案不与源电极和漏电极重叠的曝光区域。 重叠区域的厚度和曝光区域的厚度相同。

公开(公告)号：US09099438B2

公开(公告)日：2015-08-04

申请号：US13660362

申请日：2012-10-25

Applicant: Samsung Display Co., Ltd.

Inventor： Jae Woo Park ,  Do-Hyun Kim ,  Young Joo Choi ,  Dong Hoon Lee ,  Sung Haeng Cho

IPC: H01L29/10 ,  H01L29/45 ,  H01L29/49 ,  H01L29/786 ,  H01L27/12

CPC classification number: H01L27/1225 ,  H01L27/124 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/7869

Abstract: A thin film transistor array panel includes: a gate line disposed on a substrate and including a gate electrode, a semiconductor layer including an oxide semiconductor disposed on the substrate, and a data wire layer disposed on the substrate and including a data line intersecting the gate line, a source electrode connected to the data line, and a drain electrode facing the source electrode. In addition, at least one of the data line, the source electrode or the drain electrode of the data wire layer includes a barrier layer and a main wiring layer disposed on the barrier layer. The main wiring layer includes copper or a copper alloy. Also, the barrier layer includes a metal oxide, and the metal oxide includes zinc.

Abstract translation: 薄膜晶体管阵列面板包括：栅极线，设置在基板上并且包括栅电极，包括设置在基板上的氧化物半导体的半导体层以及设置在基板上的数据线层，并且包括与栅极交叉的数据线 线，连接到数据线的源电极和面对源电极的漏电极。 此外，数据线层的数据线，源电极或漏电极中的至少一个包括阻挡层和设置在阻挡层上的主配线层。 主配线层包括铜或铜合金。 此外，阻挡层包括金属氧化物，并且金属氧化物包括锌。

公开(公告)号：US08932917B2

公开(公告)日：2015-01-13

申请号：US13940761

申请日：2013-07-12

Applicant: Samsung Display Co., Ltd.

Inventor： Byoung-June Kim ,  Jae-Ho Choi ,  Chang-Oh Jeong ,  Sung-Hoon Yang ,  Je-Hun Lee ,  Do-Hyun Kim ,  Hwa-Yeul Oh ,  Yong-Mo Choi

IPC: H01L27/12 ,  H01L29/66

CPC classification number: H01L27/1255 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66765

Abstract: A manufacturing method of a thin film transistor (TFT) includes forming a gate electrode including a metal that can be combined with silicon to form silicide on a substrate and forming a gate insulation layer by supplying a gas which includes silicon to the gate electrode at a temperature below about 280° C. The method further includes forming a semiconductor on the gate insulation layer, forming a data line and a drain electrode on the semiconductor and forming a pixel electrode connected to the drain electrode.

Abstract translation: 薄膜晶体管（TFT）的制造方法包括形成包括可以与硅组合的金属的栅电极，以在衬底上形成硅化物，并通过在栅极电极中向栅电极提供包括硅的气体形成栅极绝缘层 该方法还包括在栅极绝缘层上形成半导体，在半导体上形成数据线和漏极并形成连接到漏电极的像素电极。

公开(公告)号：US20130295731A1

公开(公告)日：2013-11-07

申请号：US13940761

申请日：2013-07-12

Applicant: Samsung Display Co., Ltd.

Inventor： BYOUNG-JUNE KIM ,  Jae-Ho Choi ,  Chang-Oh Jeong ,  Sung-Hoon Yang ,  Je-Hun Lee ,  Do-Hyun Kim ,  Hwa-Yeul Oh ,  Yong-Mo Choi

IPC: H01L29/66

CPC classification number: H01L27/1255 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66765

Abstract: A manufacturing method of a thin film transistor (TFT) includes forming a gate electrode including a metal that can be combined with silicon to form silicide on a substrate and forming a gate insulation layer by supplying a gas which includes silicon to the gate electrode at a temperature below about 280° C. The method further includes forming a semiconductor on the gate insulation layer, forming a data line and a drain electrode on the semiconductor and forming a pixel electrode connected to the drain electrode.

Abstract translation: 薄膜晶体管（TFT）的制造方法包括形成包括可以与硅组合的金属的栅电极，以在衬底上形成硅化物，并通过在栅极电极中向栅电极提供包括硅的气体形成栅极绝缘层 该方法还包括在栅极绝缘层上形成半导体，在半导体上形成数据线和漏极并形成连接到漏电极的像素电极。