公开(公告)号：US11231824B2

公开(公告)日：2022-01-25

申请号：US16840891

申请日：2020-04-06

Applicant: Samsung Display Co., Ltd.

Inventor： Gwang Bum Ko ,  Hyun Jae Na

IPC: G06F3/045 ,  G06F3/044 ,  G06F3/047

Abstract: A touch panel including a sensing cell and a sensing line disposed on a transparent substrate. Each of the sensing cell and the sensing line includes at least one pattern line. The at least one pattern line includes unit patterns, each of the unit patterns including a first line extending in a first direction, a second line connected to the first line and extending in a second direction intersecting the first direction, a third line connected to the first line and extending in a third direction intersecting the first direction, and a fourth line connected to the third line and extending in the first direction. The first line, the second line, the third line, and an extension of the fourth line form a trapezoid. The unit patterns are repeatedly arranged and adjacent unit patterns are connected each other.

公开(公告)号：US10861978B2

公开(公告)日：2020-12-08

申请号：US16231781

申请日：2018-12-24

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yong Su Lee ,  Yoon Ho Khang ,  Dong Jo Kim ,  Hyun Jae Na ,  Sang Ho Park ,  Se Hwan Yu ,  Chong Sup Chang ,  Dae Ho Kim ,  Jae Neung Kim ,  Myoung Geun Cha ,  Sang Gab Kim ,  Yu-Gwang Jeong

IPC: H01L27/00 ,  H01L29/00 ,  H01L29/786 ,  H01L27/12 ,  H01L29/66 ,  H01L29/417 ,  H01L27/32

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

公开(公告)号：US10705663B2

公开(公告)日：2020-07-07

申请号：US16457329

申请日：2019-06-28

Applicant: Samsung Display Co., Ltd.

Inventor： Soon Sung Ahn ,  Hyoung Wook Jang ,  Hyun Jae Na ,  Mu Gyeom Kim

IPC: G06F3/044 ,  G06K9/00

Abstract: A touch screen including a substrate that includes an active area and a non-active area adjacent to the active area, the active area including at least one fingerprint recognition area; touch sensing electrodes including first sensing electrodes arranged in the active area, and at least one second sensing electrode arranged in the fingerprint recognition area, the second sensing electrode configured for sensing a touch and recognizing a fingerprint; and a pad portion provided with a plurality of pads which are electrically connected to respective sensing electrodes, wherein the at least one second sensing electrode includes: a plurality of sub electrodes extending in a direction inclined with respect to an edge portion of the active area; and a plurality of fingerprint recognition lines connecting the sub electrodes to the pad portion, and the fingerprint recognition lines arranged in a same fingerprint recognition area extend in a same direction.

公开(公告)号：US10592052B2

公开(公告)日：2020-03-17

申请号：US16573461

申请日：2019-09-17

Applicant: Samsung Display Co., Ltd.

Inventor： Gwang Bum Ko ,  Hyun Jae Na ,  Hyoung Wook Jang ,  Ye Ri Jeong ,  Jeong Yun Han

IPC: G06F3/041 ,  G06F3/044

Abstract: A touch sensor includes: a plurality of first sensor electrode columns disposed in a sensing area, the plurality of first sensor electrode columns each including one or more first sensor electrodes; a plurality of second sensor electrode columns alternately disposed with the first sensor electrode columns in the sensing area, the plurality of second sensor electrode columns each including a plurality of second sensor electrodes having a length defined by a longitudinal axis and a width extending in a direction across the length; a plurality of lines connected to the first sensor electrode columns and the second sensor electrode columns; and a pad unit including a plurality of pads connected to the lines, wherein at least some of the second sensor electrodes have a width that varies along the longitudinal axis of its respective second electrodes.

公开(公告)号：US20190312147A1

公开(公告)日：2019-10-10

申请号：US16231781

申请日：2018-12-24

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Yong Su Lee ,  Yoon Ho Khang ,  Dong Jo Kim ,  Hyun Jae Na ,  Sang Ho Park ,  Se Hwan Yu ,  Chong Sup Chang ,  Dae Ho Kim ,  Jae Neung Kim ,  Myoung Geun Cha ,  Sang Gab Kim ,  Yu-Gwang Jeong

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/417 ,  H01L29/66

Abstract: A thin film transistor according to an exemplary embodiment of the present invention includes an oxide semiconductor. A source electrode and a drain electrode face each other. The source electrode and the drain electrode are positioned at two opposite sides, respectively, of the oxide semiconductor. A low conductive region is positioned between the source electrode or the drain electrode and the oxide semiconductor. An insulating layer is positioned on the oxide semiconductor and the low conductive region. A gate electrode is positioned on the insulating layer. The insulating layer covers the oxide semiconductor and the low conductive region. A carrier concentration of the low conductive region is lower than a carrier concentration of the source electrode or the drain electrode.

公开(公告)号：US20170075449A1

公开(公告)日：2017-03-16

申请号：US15132699

申请日：2016-04-19

Applicant: Samsung Display Co., Ltd.

Inventor： Gwang Bum KO ,  Hyun Jae Na

IPC: G06F3/044 ,  G06F3/047

CPC classification number: G06F3/044 ,  G06F3/047 ,  G06F2203/04112

Abstract: A touch panel includes a sensing cell and a sensing line disposed on a transparent substrate. Each of the sensing cell and the sensing line includes at least one pattern line. The at least one pattern line includes unit patterns, each of the unit patterns including a first line extending in a first direction, a second line connected to the first line and extending in a second direction intersecting the first direction, a third line connected to the first line and extending in a third direction intersecting the first direction, and a fourth line connected to the third line and extending in the first direction. The first line, the second line, the third line, and an extension of the fourth line form a trapezoid. The unit patterns are repeatedly arranged and adjacent unit patterns are connected each other.

Abstract translation: 触摸面板包括感测单元和设置在透明基板上的感测线。 每个感测单元和感测线包括至少一个图案线。 所述至少一个图案线包括单位图案，每个所述单元图案包括沿第一方向延伸的第一线，连接到所述第一线并沿与所述第一方向相交的第二方向延伸的第二线，连接到所述第一线的第三线 第一线并且沿与第一方向相交的第三方向延伸，以及连接到第三线并沿第一方向延伸的第四线。 第一行，第二行，第三行和第四行的扩展形成梯形。 重复布置单元图案，并且相邻的单元图案彼此连接。

公开(公告)号：US09263467B2

公开(公告)日：2016-02-16

申请号：US14466665

申请日：2014-08-22

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Sang Ho Park ,  Yoon Ho Khang ,  Se Hwan Yu ,  Yong Su Lee ,  Chong Sup Chang ,  Myoung Geun Cha ,  Hyun Jae Na

IPC: H01L29/04 ,  H01L31/036 ,  H01L31/0376 ,  H01L31/20 ,  H01L27/12 ,  H01L29/786 ,  H01L29/417 ,  H01L29/45

CPC classification number: H01L27/124 ,  H01L27/1214 ,  H01L29/41758 ,  H01L29/458 ,  H01L29/78642 ,  H01L29/78669 ,  H01L29/78678

Abstract: A thin film transistor array panel according to an exemplary embodiment of the present disclosure includes: an insulating substrate; a gate electrode disposed on the insulating substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor; an ohmic contact layer disposed at an interface between at least one of the source and drain electrodes and the semiconductor. Surface heights of the source and drain electrodes different, while surface heights of the semiconductor and the ohmic contact layer are the same. The ohmic contact layer is made of a silicide of a metal used for the source and drain electrodes.

Abstract translation: 根据本公开的示例性实施例的薄膜晶体管阵列面板包括：绝缘基板; 设置在所述绝缘基板上的栅电极; 设置在栅电极上的栅极绝缘层; 设置在所述栅极绝缘层上的半导体; 设置在半导体上的源电极和漏电极; 欧姆接触层设置在源电极和漏电极中的至少一个与半导体之间的界面处。 源极和漏极的表面高度不同，而半导体和欧姆接触层的表面高度相同。 欧姆接触层由用于源极和漏极的金属的硅化物制成。

公开(公告)号：US20150069399A1

公开(公告)日：2015-03-12

申请号：US14249329

申请日：2014-04-09

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Seung-Hwan Cho ,  Young Ki Shin ,  Dong Hwan Shim ,  Yoon Ho Khang ,  Hyun Jae Na

IPC: H01L29/786 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L29/66969 ,  H01L29/78696

Abstract: A thin film transistor includes: a first semiconductor layer; a second semiconductor layer disposed on the first semiconductor layer; and a pair of source region and drain region formed by doping both sides of the first semiconductor layer and the second semiconductor layer with impurities, and the source region includes a first source layer on the same plane as the first semiconductor layer and a second source layer on the same plane as the second semiconductor layer, and the drain region includes a first drain layer on the same plane as the first semiconductor layer and a second drain layer on the same plane as the second semiconductor layer, and only one of the first semiconductor layer and the second semiconductor layer is a transistor channel layer.

Abstract translation: 薄膜晶体管包括：第一半导体层; 设置在所述第一半导体层上的第二半导体层; 以及通过用杂质掺杂第一半导体层和第二半导体层的两侧而形成的一对源区和漏区，源极区包括与第一半导体层在同一平面上的第一源极层和第二源极层 在与第二半导体层相同的平面上，漏区包括与第一半导体层相同的平面上的第一漏极层和与第二半导体层在同一平面上的第二漏极层，并且仅第一半导体 层，第二半导体层是晶体管沟道层。

公开(公告)号：US20140183522A1

公开(公告)日：2014-07-03

申请号：US14063774

申请日：2013-10-25

Applicant: Samsung Display Co., Ltd.

Inventor： Myoung Geun Cha ,  Yong Su Lee ,  Yoon Ho Khang ,  Hyun Jae Na ,  Se Hwan Yu ,  Jong Chan Lee ,  Dong Hwan Shim

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L27/1222 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78621 ,  H01L29/78633 ,  H01L29/7869

Abstract: A thin film transistor array panel including a substrate; a channel region disposed on the substrate and including oxide semiconductor disposed on the substrate; a source electrode and a drain electrode connected to the oxide semiconductor and facing each other at both sides, centered on the oxide semiconductor; an insulating layer disposed on the oxide semiconductor; and a gate electrode disposed on the insulating layer. The drain electrode includes a first drain region and a second drain region; the charge mobility of the first drain region is greater than that of the second drain region, the source electrode includes a first source region and a second source region, and the charge mobility of the first source region is greater than that of the second source region.

Abstract translation: 一种薄膜晶体管阵列面板，包括基板; 设置在所述基板上并且包括设置在所述基板上的氧化物半导体的沟道区; 连接到所述氧化物半导体并且以所述氧化物半导体为中心的两侧面对的源电极和漏电极; 设置在所述氧化物半导体上的绝缘层; 以及设置在所述绝缘层上的栅电极。 漏极包括第一漏区和第二漏区; 第一漏极区域的电荷迁移率大于第二漏极区域的电荷迁移率，源电极包括第一源极区域和第二源极区域，并且第一源极区域的电荷迁移率大于第二源极区域的电荷迁移率 。

公开(公告)号：US20140138684A1

公开(公告)日：2014-05-22

申请号：US14166183

申请日：2014-01-28

Applicant: Samsung Display Co., Ltd.

Inventor： YONG SU LEE ,  Yoon Ho Khang ,  Dong Jo Kim ,  Hyun Jae Na ,  Sang Ho Park ,  Se Hwan Yu ,  Chong Sup Chang

IPC: H01L27/12

CPC classification number: H01L29/7869 ,  H01L21/0262 ,  H01L21/385 ,  H01L21/441 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/1259 ,  H01L27/1288 ,  H01L29/41733 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78633 ,  H01L29/78696

Abstract: A thin film transistor, a thin film transistor array panel including the same, and a method of manufacturing the same are provided, wherein the thin film transistor includes a channel region including an oxide semiconductor, a source region and a drain region connected to the channel region and facing each other at both sides with respect to the channel region, an insulating layer positioned on the channel region, and a gate electrode positioned on the insulating layer, wherein an edge boundary of the gate electrode and an edge boundary of the channel region are substantially aligned.

Abstract translation: 提供一种薄膜晶体管，包括该薄膜晶体管的薄膜晶体管阵列面板及其制造方法，其中薄膜晶体管包括沟道区，该沟道区包括氧化物半导体，源极区和连接到沟道的漏极区 区域，并且相对于沟道区域在两侧面对，位于沟道区域上的绝缘层和位于绝缘层上的栅电极，其中栅电极的边缘边界和沟道区域的边缘边界 基本对齐。