公开(公告)号：US20210104524A1

公开(公告)日：2021-04-08

申请号：US16898719

申请日：2020-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoon Tae HWANG ,  Sunjung LEE ,  Heonbok LEE ,  Geunwoo KIM ,  Wandon KIM

IPC: H01L27/092 ,  H01L21/8238

Abstract: A semiconductor device includes a first and second channel patterns on a substrate, each of the first and second channel patterns including vertically-stacked semiconductor patterns; a first source/drain pattern connected to the first channel pattern; a second source/drain pattern connected to the second channel pattern, the first and second source/drain patterns having different conductivity types from each other; a first contact plug inserted in the first source/drain pattern, and a second contact plug inserted in the second source/drain pattern; a first interface layer interposed between the first source/drain pattern and the first contact plug; and a second interface layer interposed between the second source/drain pattern and the second contact plug, the first and second interface layers including different metallic elements from each other, a bottom portion of the second interface layer being positioned at a level that is lower than a bottom surface of a topmost one of the semiconductor patterns.

公开(公告)号：US20210066289A1

公开(公告)日：2021-03-04

申请号：US16851476

申请日：2020-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sunyoung NOH ,  Wandon KIM ,  Hyunbae LEE ,  Donggon YOO ,  Dong-Chan LIM

IPC: H01L27/088 ,  H01L23/528 ,  H01L23/532 ,  H01L21/8234 ,  H01L21/321 ,  H01L21/768 ,  H01L29/06

Abstract: A semiconductor device includes an interlayer dielectric layer on a substrate, a first connection line that fills a first trench of the interlayer dielectric layer, the first trench having a first width, and a second connection line that fills a second trench of the interlayer dielectric layer, the second trench having a second width greater than the first width, and the second connection line including a first metal layer that covers an inner sidewall of the second trench, a barrier layer that covers a bottom surface of the second trench, and a second metal layer on the first metal layer and the barrier layer, the first connection line and the first metal layer include a first metal, and the second metal layer includes a second metal different from the first metal.

公开(公告)号：US20200243374A1

公开(公告)日：2020-07-30

申请号：US16539064

申请日：2019-08-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Seung Hoon CHOI ,  Jaeung KOO ,  Kwansung KIM ,  Bo Yun KIM ,  Wandon KIM ,  Boun YOON ,  Jeonghyuk YIM ,  Yeryung JEON

IPC: H01L21/768 ,  H01L27/105 ,  H01L21/3105 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device and a method of fabricating a semiconductor device, the semiconductor device including a semiconductor substrate including a first region and a second region; an interlayer insulating layer on the semiconductor substrate, the interlayer insulating layer including a first opening on the first region and having a first width; and a second opening on the second region and having a second width, the second width being greater than the first width; at least one first metal pattern filling the first opening; a second metal pattern in the second opening; and a filling pattern on the second metal pattern in the second opening, wherein the at least one first metal pattern and the second metal pattern each include a same first metal material, and the filling pattern is formed of a non-metal material.

公开(公告)号：US20170005175A1

公开(公告)日：2017-01-05

申请号：US15186982

申请日：2016-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyeol SONG ,  Wandon KIM ,  Hoonjoo NA ,  Suyoung BAE ,  Hyeok-Jun SON ,  Sangjin HYUN

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/78 ,  H01L27/085

CPC classification number: H01L29/517 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/085 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518

Abstract: A semiconductor device includes a semiconductor substrate including multiple active regions having a common conductivity type and separate, respective gate electrodes on the separate active regions. Different high-k dielectric layers may he between the separate active regions and the respective gate electrodes on the active regions. Different quantities of high-k dielectric layers may be between the separate active regions and the respective gate electrodes on the active regions. The different high-k dielectric layers may include different work-function adjusting materials.

Abstract translation: 半导体器件包括半导体衬底，该半导体衬底包括具有共同导电类型的多个有源区和在分离的有源区上分开的相应的栅电极。 不同的高k电介质层可以在分离的有源区和有源区上的相应栅电极之间。 不同数量的高k电介质层可以在分离的有源区域和有源区域上的相应栅电极之间。 不同的高k电介质层可以包括不同的功函调整材料。

公开(公告)号：US20250096134A1

公开(公告)日：2025-03-20

申请号：US18650288

申请日：2024-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geunwoo KIM ,  Hyunwoo KANG ,  Mingyu KIM ,  Wandon KIM ,  Wonkeun CHUNG ,  Hyoseok CHOI

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786

Abstract: An integrated circuit device may include a source/drain contact insulation layer on a lower structure, a source/drain contact via penetrating through the source/drain contact insulation layer, an interconnect wiring insulation layer on the source/drain contact insulation layer and including an interconnect wiring trench exposing a top surface of the source/drain contact via, a first interconnect wiring layer covering a lower portion of a sidewall of the interconnect wiring trench and including a first precursor, and a second interconnect wiring layer on the first interconnect wiring layer. The second interconnect wiring layer may cover an upper portion of a sidewall of the interconnect wiring trench and may include a second precursor. A crystal grain size of the second precursor may be larger than a crystal grain size of the first precursor.

公开(公告)号：US20230118906A1

公开(公告)日：2023-04-20

申请号：US18085871

申请日：2022-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yoontae HWANG ,  Wandon KIM ,  Geunwoo KIM ,  Heonbok LEE ,  Taegon KIM ,  Hanki LEE

IPC: H01L29/45 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L21/285 ,  H01L29/08 ,  H01L23/532 ,  H01L23/485 ,  H01L23/522

Abstract: A semiconductor device including a substrate; a fin active region on the substrate and extending in a first direction; a gate structure extending across the fin active region and extending in a second direction; a source/drain region in the fin active region on a side of the gate structure; an insulating structure covering the gate structure and the source/drain region; and contact structures penetrating through the insulating structure and respectively connected to the source/drain region and the gate structure, wherein one of the contact structures includes a seed layer on the gate structure or the source/drain regions and including lower and upper regions, the lower region having a first grain size and the upper region being amorphous or having a grain size different from the first grain size, and a contact plug on an upper region of the seed layer and having a second grain size.

公开(公告)号：US20230012516A1

公开(公告)日：2023-01-19

申请号：US17672033

申请日：2022-02-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoontae HWANG ,  Geunwoo KIM ,  Wandon KIM ,  Hyunbae LEE

IPC: H01L29/417 ,  H01L29/45 ,  H01L23/522

Abstract: An integrated circuit (IC) device includes a conductive region including a first metal on a substrate. An insulating film is on the conductive region. A conductive plug including a second metal passes through the insulating film and extends in a vertical direction. A conductive barrier pattern is between the conductive region and the conductive plug. The conductive barrier pattern has a first surface in contact with the conductive region and a second surface in contact with the conductive plug. A bottom surface and a lower sidewall of the conductive plug are in contact with the conductive barrier pattern, and an upper sidewall of the conductive plug is in contact with the insulating film. The conductive barrier pattern includes a vertical barrier portion between the insulating film and the conductive plug, and the vertical barrier portion has a width tapering along a first direction away from the conductive region.

公开(公告)号：US20220199522A1

公开(公告)日：2022-06-23

申请号：US17373573

申请日：2021-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eui Bok LEE ,  Donggon YOO ,  Wandon KIM

IPC: H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/06

Abstract: A semiconductor device including transistors on a substrate, a first interlayer insulating layer on the transistors, a first lower interconnection line and a second lower interconnection line in an upper portion of the first interlayer insulating layer, a dielectric layer being selectively on a top surface of the first interlayer insulating layer except top surfaces of the first and second lower interconnection lines, an etch stop layer on the first and second lower interconnection lines and the dielectric layer, a second interlayer insulating layer on the etch stop layer, and an upper interconnection line in the second interlayer insulating layer may be provided.

公开(公告)号：US20150294873A1

公开(公告)日：2015-10-15

申请号：US14636257

申请日：2015-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Huyong LEE ,  Jae-Jung KIM ,  Wandon KIM ,  Sangjin HYUN

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L21/283

CPC classification number: H01L27/11521 ,  H01L29/40114 ,  H01L29/42336 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785

Abstract: Provided is a method of fabricating a semiconductor device, including forming an interlayered insulating layer having an opening, on a substrate; sequentially forming a first conductive pattern, a barrier pattern, and a second conductive pattern on bottom and side surfaces of the opening; and nitrifying an upper portion of the second conductive pattern to form a metal nitride layer that is spaced apart from the first conductive pattern.

Abstract translation: 提供一种制造半导体器件的方法，包括在衬底上形成具有开口的层间绝缘层; 在开口的底部和侧表面上依次形成第一导电图案，阻挡图案和第二导电图案; 并且硝化第二导电图案的上部以形成与第一导电图案间隔开的金属氮化物层。