公开(公告)号：US20230328961A1

公开(公告)日：2023-10-12

申请号：US17987011

申请日：2022-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： MIN HEE CHO ,  KISEOK LEE ,  WONSOK LEE

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/10897 ,  H01L27/10873

Abstract: A semiconductor device includes a first conductive line that extends in a first horizontal direction, a plurality of semiconductor patterns on the first conductive line and spaced apart from each other in the first horizontal direction wherein each of the semiconductor patterns includes a first vertical part and a second vertical part that are opposite to each other in the first horizontal direction, a second conductive line that extends in a second horizontal direction between the first vertical part and the second vertical part of each of the semiconductor patterns, the second horizontal direction intersecting the first horizontal direction, a gate dielectric pattern between the first vertical part and the second vertical part and between the second vertical part and the second conductive line, and a blocking pattern between neighboring semiconductor patterns.

公开(公告)号：US20230187548A1

公开(公告)日：2023-06-15

申请号：US17976955

申请日：2022-10-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： WONSOK LEE ,  MIN TAE RYU ,  SUNGWON YOO ,  KISEOK LEE ,  MIN HEE CHO

IPC: H01L29/78 ,  G11C5/06 ,  H01L29/08 ,  H01L29/10 ,  H01L27/105

CPC classification number: H01L29/7827 ,  G11C5/063 ,  H01L27/1052 ,  H01L29/0847 ,  H01L29/1033

Abstract: A semiconductor memory device includes bit lines disposed on a substrate and extending in a first direction in parallel to each other, a hydrogen supply insulating layer including hydrogen and filling a space between the bit lines, a source pattern located on each of the bit lines and being in partial contact with the hydrogen supply insulating layer, a hydrogen diffusion barrier layer covering a top surface of the hydrogen supply insulating layer and being in contact with a side surface of the source pattern, a first channel pattern located on the source pattern, a first word line being adjacent to a side surface of the first channel pattern and crossing over the bit lines, and a landing pad on the first channel pattern.

公开(公告)号：US20230089688A1

公开(公告)日：2023-03-23

申请号：US17705991

申请日：2022-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNHYEOK AHN ,  HUIJUNG KIM ,  KISEOK LEE ,  MYEONGDONG LEE

IPC: H01L27/108

Abstract: A semiconductor device includes; an active region defined by an isolation film on a substrate, a word line in the substrate, the word line extending in a first direction and crossing the active region, a bit line above the word line and extending in a second direction, a contact between bit lines adjacent in the first direction, the contact connecting the active region and extending in a vertical direction, and a contact fence disposed on each of opposing side surfaces of the contact in the second direction and extending in the vertical direction, wherein the active region has a bar shape extending oblique to the first direction, and the contact fence includes a carbon-containing insulating film.

公开(公告)号：US20210159277A1

公开(公告)日：2021-05-27

申请号：US17167851

申请日：2021-02-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： HUI-JUNG KIM ,  KISEOK LEE ,  KEUNNAM KIM ,  YOOSANG HWANG

IPC: H01L27/24 ,  H01L45/00

Abstract: Disclosed is a variable resistance memory device including a first conductive line extending in a first direction parallel to a top surface of the substrate, memory cells spaced apart from each other in the first direction on a side of the first conductive line and connected to the first conductive line, and second conductive lines respectively connected to the memory cells. Each second conductive line is spaced apart in a second direction from the first conductive line. The second direction is parallel to the top surface of the substrate and intersects the first direction. The second conductive lines extend in a third direction perpendicular to the top surface of the substrate and are spaced apart from each other in the first direction. Each memory cell includes a variable resistance element and a select element that are positioned at a same level horizontally arranged in the second direction.

公开(公告)号：US20210143154A1

公开(公告)日：2021-05-13

申请号：US17126195

申请日：2020-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： KISEOK LEE ,  BONG-SOO KIM ,  JIYOUNG KIM ,  HUI-JUNG KIM ,  SEOKHAN PARK ,  HUNKOOK LEE ,  YOOSANG HWANG

IPC: H01L27/108 ,  H01L23/528 ,  H01L29/08 ,  H01L29/165 ,  H01L29/10

Abstract: Semiconductor memory devices may include first and second stacks on a substrate and first and second interconnection lines on the first and second stacks. Each of the first and second stacks may include semiconductor patterns vertically stacked on the substrate, conductive lines connected to the semiconductor patterns, respectively, and a gate electrode that is adjacent to the semiconductor patterns and extends in a vertical direction. The first stack may include a first conductive line and a first gate electrode, and the second stack may include a second conductive line and a second gate electrode. Lower surfaces of the first and second conductive lines may be coplanar. The first interconnection line may be electrically connected to at least one of the first and second conductive lines. The second interconnection line may be electrically connected to at least one of the first and second gate electrodes.

公开(公告)号：US20200006434A1

公开(公告)日：2020-01-02

申请号：US16455791

申请日：2019-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： HUI-JUNG KIM ,  KISEOK LEE ,  KEUNNAM KIM ,  YOOSANG HWANG

IPC: H01L27/24 ,  H01L45/00

Abstract: Disclosed is a variable resistance memory device including a first conductive line extending in a first direction parallel to a top surface of the substrate, memory cells spaced apart from each other in the first direction on a side of the first conductive line and connected to the first conductive line, and second conductive lines respectively connected to the memory cells. Each second conductive line is spaced apart in a second direction from the first conductive line. The second direction is parallel to the top surface of the substrate and intersects the first direction. The second conductive lines extend in a third direction perpendicular to the top surface of the substrate and are spaced apart from each other in the first direction. Each memory cell includes a variable resistance element and a select element that are positioned at a same level horizontally arranged in the second direction.