公开(公告)号：US20170011794A1

公开(公告)日：2017-01-12

申请号：US15274852

申请日：2016-09-23

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji NII ,  Shigeki OBAYASHI ,  Hiroshi MAKINO ,  Koichiro ISHIBASHI ,  Hirofumi SHINOHARA

IPC: G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C11/412

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract translation: 单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。 在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。 即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。

公开(公告)号：US20160247569A1

公开(公告)日：2016-08-25

申请号：US15004990

申请日：2016-01-24

Applicant: Renesas Electronics Corporation

Inventor： Koji NII

IPC: G11C15/04

CPC classification number: G11C15/04 ,  H01L27/0207 ,  H01L27/1104

Abstract: A semiconductor memory device capable of a high-accuracy data search is provided. Each of the memory cells can hold two bits of information and includes a first cell and a second cell. The semiconductor memory device also includes a match line and a search line pair to transfer search data. The semiconductor memory device further includes a logic operation cell to drive the match line based on comparison results between information held in the first and the second cell and search data transferred by the search line pair and a search line driver to drive the search line pair. In a state with the search line pair precharged to a third voltage between a first voltage and a second voltage, the search line driver drives, according to the search data, one and the other search line included in the search line pair to the first and the second voltage, respectively.

Abstract translation: 提供能够进行高精度数据搜索的半导体存储器件。 每个存储器单元可以容纳两位信息，并且包括第一单元和第二单元。 半导体存储器件还包括匹配线和搜索线对以传送搜索数据。 半导体存储装置还包括：逻辑运算单元，其基于在第一和第二单元中保持的信息与由搜索线对传送的搜索数据之间的比较结果和搜索线驱动器驱动搜索线对，来驱动匹配线。 在搜索线对被预先充电到第一电压和第二电压之间的第三电压的状态下，搜索线驱动器根据搜索数据将包括在搜索线对中的一条和另一条搜索线驱动到第一和第二电压， 分别为第二电压。

公开(公告)号：US20160109915A1

公开(公告)日：2016-04-21

申请号：US14976775

申请日：2015-12-21

Applicant: Renesas Electronics Corporation

Inventor： Masanori ISODA ,  Hidehiro FUJIWARA ,  Koji NII

IPC: G06F1/26 ,  G06F21/44

CPC classification number: G06F1/26 ,  G06F11/2247 ,  G06F12/14 ,  G06F21/44 ,  G06F21/71 ,  G06F21/78 ,  G06F2212/1052 ,  G11C5/14 ,  G11C8/20 ,  G11C11/417

Abstract: A semiconductor device includes an identification information generation circuit having a power supply control circuit whose output voltage is controlled by a control signal, and a memory array having a first cell power line and a second cell power line. The power supply control circuit outputs a first supply voltage and a second supply voltage to a first cell power line and a second power line, respectively, when the control signal is in a first state, and outputs an intermediate voltage to the first cell power line and the second cell power line when the control signal is in a second state.

公开(公告)号：US20160078925A1

公开(公告)日：2016-03-17

申请号：US14942822

申请日：2015-11-16

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Koji NII ,  Shigeki OBAYASHI ,  Hiroshi MAKINO ,  Koichiro ISHIBASHI ,  Hirofumi SHINOHARA

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/063 ,  G11C11/412

Abstract: Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a floating state according to the bit line potential on a selected column and has the voltage level changed, and a latching capability of a selected memory cell is reduced to write data fast. Even with a low power supply voltage, a static semiconductor memory device that can stably perform write and read of data is implemented.

Abstract translation: 单元电源线被布置用于存储单元列，并且分别根据相应列中的位线的电压电平来调整单元电源线的阻抗或电压电平。 在数据写入操作中，根据所选列的位线电位将单元电源线强制为浮置状态，并且电压电平改变，并且减小所选存储单元的锁存能力以快速写入数据。 即使使用低电源电压，也可以实现能够稳定地执行数据的写入和读取的静态半导体存储器件。

公开(公告)号：US20150380076A1

公开(公告)日：2015-12-31

申请号：US14835127

申请日：2015-08-25

Applicant: Renesas Electronics Corporation

Inventor： Noriaki MAEDA ,  Yoshihiro SHINOZAKI ,  Masanao YAMAOKA ,  Yasuhisa SHIMAZAKI ,  Masanori ISODA ,  Koji NII

IPC: G11C11/412

CPC classification number: G11C11/412 ,  G11C5/063 ,  G11C5/14 ,  G11C11/419 ,  H01L27/11 ,  H01L27/1104

Abstract: The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

Abstract translation: 本发明提供了一种具有SRAM的半导体集成电路器件，其满足对具有低电源电压的SNM和写入裕度两者的要求。 半导体集成电路装置包括：与多个字线和多个互补位线对应地设置的多个静态存储单元; 多个存储单元电源线，其各自向连接到多个互补位线的多个存储器单元中的每一个提供工作电压; 多个电源电路由电阻单元构成，每个电阻单元各自向存储单元电源线提供电源电压; 以及预充电电路，其向互补位线提供与电源电压相对应的预充电电压，其中使存储单元电源线具有耦合电容，从而在相应的互补位线上传输写信号。

公开(公告)号：US20140293680A1

公开(公告)日：2014-10-02

申请号：US14263307

申请日：2014-04-28

Applicant: Renesas Electronics Corporation

Inventor： Koji NII ,  Shigeki OHBAYASHI ,  Yasumasa TSUKAMOTO ,  Makoto YABUUCHI

IPC: G11C11/417 ,  G11C5/14 ,  G11C5/06

CPC classification number: G11C11/419 ,  G11C5/06 ,  G11C5/14 ,  G11C8/08 ,  G11C11/417 ,  G11C11/418

Abstract: In a semiconductor memory device, static memory cells are arranged in rows and columns, word lines correspond to respective memory cell rows, and word line drivers drive correspond to word lines. Cell power supply lines correspond to respective memory cell columns and are coupled to cell power supply nodes of a memory cell in a corresponding column. Down power supply lines are arranged corresponding to respective memory cell columns, maintained at ground voltage in data reading and rendered electrically floating in data writing. Write assist elements are arranged corresponding to the cell power supply lines, and according to a write column instruction signal for stopping supply of a cell power supply voltage to the cell power supply line in a selected column, and for coupling the cell power supply line arranged corresponding to the selected column at least to the down power supply line on the corresponding column.

Abstract translation: 在半导体存储器件中，静态存储单元以行和列排列，字线对应于相应的存储单元行，并且字线驱动器对应于字线。 单元电源线对应于相应的存储单元列并且耦合到相应列中的存储器单元的单元电源节点。 向下电源线被布置成对应于相应的存储单元列，保持在数据读取中的接地电压并且在数据写入中被电浮动。 写入辅助元件对应于单电池电源线布置，并且根据写入列指示信号，用于停止向所选列中的单元电源线提供单元电源电压，并且用于耦合布置的单元电源线 对应于所选列至少至相应列上的下电源线。