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公开(公告)号：US10027026B2
公开(公告)日：2018-07-17
申请号：US14489715
申请日：2014-09-18
Applicant: Raytheon Company
Inventor： Harry B. Marr
CPC classification number: H01Q3/00 , H01Q3/26 , H04B7/0617 , H04B7/0634
Abstract: A beamforming system includes a plurality of channelizers and a channel switching module in signal communication with the channelizers. Each channelizer is configured to receive a respective input radio frequency signal and to generate a plurality of respective channels in response to downsampling the respective input radio frequency signal. The channel switching module includes a channel combining circuit configured to selectively combine a common channel generated by each channelizer to form at least one steered analog beam.
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22.发明申请公开(公告)号：US20180106884A1
公开(公告)日：2018-04-19
申请号：US15295084
申请日：2016-10-17
Applicant: RAYTHEON COMPANY
Inventor： Harry B. Marr , John P. Gianvittorio , Jeffrey Caldwell , Samuel E. Parker , John Cangeme
IPC: G01S7/35
Abstract: Method and apparatus for leakage signal cancellation in a simultaneous transmit and receive RF system includes: generating a digital transmit signal for transmission from the system; receiving a receive signal produced by reflection of the transmit signal from an object or generated by a second RF system; adaptively filtering the transmit signal by an adaptive finite input response (FIR) filter; calculating filter coefficients for the adaptive FIR filter in real-time at a different sampling rate; adaptively inputting the calculated filter coefficients to the adaptive FIR filter to generate a cancellation signal in real-time; and applying the cancellation signal to the receive signal to cancel leakage in the receive signal to generate an optimum receive signal.
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公开(公告)号：US09626533B2
公开(公告)日：2017-04-18
申请号：US14849529
申请日：2015-09-09
Applicant: Raytheon Company
Inventor： Denpol Kultran , Won Chon , Harry B. Marr
Abstract: There is provided a programmable multiplier circuit for multiplying an input voltage signal by a binary coefficient, the multiplier circuit including a transconductor including a first amplifying transistor configured to convert the input voltage signal to a current signal, the first amplifying transistor having a gate configured to receive the input voltage signal, and a coefficient multiplier coupled to the transconductor and configured to multiply the current signal by the binary coefficient to generate an amplified current signal.
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公开(公告)号：US20170070212A1
公开(公告)日：2017-03-09
申请号：US14849524
申请日：2015-09-09
Applicant: Raytheon Company
Inventor： Denpol Kultran , Richard T. Hennegan , Harry B. Marr
Abstract: There is provided a finite impulse response (FIR) filter for filtering an input voltage signal to generate an output current signal, the FIR filter including a plurality of sample and hold (SH) circuits configured to simultaneously receive the input voltage signal, to sample the input voltage signal at successive sample times according to a sample clock, and to generate a plurality of sampled voltage signals, and a plurality of programmable analog multipliers coupled to the plurality of SH circuits and configured to multiply the plurality of sampled voltage signals by a plurality of binary multiplication factors to generate the output current signal.
Abstract translation: 提供了用于对输入电压信号进行滤波以产生输出电流信号的有限脉冲响应（FIR）滤波器，FIR滤波器包括被配置为同时接收输入电压信号的多个采样和保持（SH）电路，以对 输入电压信号，根据采样时钟连续采样时间，并产生多个采样电压信号;以及多个可编程模拟乘法器，耦合到多个SH电路，并被配置为将多个采样电压信号乘以多个 的二进制乘法因子来产生输出电流信号。
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公开(公告)号：US20170070210A1
公开(公告)日：2017-03-09
申请号：US14849529
申请日：2015-09-09
Applicant: Raytheon Company
Inventor： Denpol Kultran , Won Chon , Harry B. Marr
IPC: H03H15/00
Abstract: There is provided a programmable multiplier circuit for multiplying an input voltage signal by a binary coefficient, the multiplier circuit including a transconductor including a first amplifying transistor configured to convert the input voltage signal to a current signal, the first amplifying transistor having a gate configured to receive the input voltage signal, and a coefficient multiplier coupled to the transconductor and configured to multiply the current signal by the binary coefficient to generate an amplified current signal.
Abstract translation: 提供了一种用于将输入电压信号乘以二进制系数的可编程乘法器电路，所述乘法器电路包括跨导体，其包括被配置为将输入电压信号转换为电流信号的第一放大晶体管，所述第一放大晶体管具有被配置为 接收所述输入电压信号，以及系数乘法器，耦合到所述跨导体并且被配置为将所述电流信号乘以所述二进制系数以产生放大的电流信号。
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Patent Agency Ranking
26.发明申请公开(公告)号：US20150147985A1
公开(公告)日：2015-05-28
申请号：US14091781
申请日：2013-11-27
Applicant: RAYTHEON COMPANY
Inventor： Harry B. Marr , Daniel Thompson , Jeffery J. Logan
IPC: H04B1/00
CPC classification number: G06F1/0321
Abstract: Described herein are methods and systems capable of generating weighted parameter sets, which can be randomly addressed for dictating a waveform of each pulse to be generated by using a probability distribution function loader to load a memory table with waveform parameter values, wherein the values are loaded according to a weighted probability distribution function. Each value is then randomly addressed in the memory table and/or randomly selected from the memory table by a random number generator and fed into a signal generation circuit for creation of the waveform to be transmitted.
Abstract translation: 这里描述的是能够生成加权参数集的方法和系统，其可以被随机地寻址以指定要通过使用概率分布函数加载器来加载具有波形参数值的存储表来生成的每个脉冲的波形，其中加载值 根据加权概率分布函数。 然后，每个值在存储器表中随机地被寻址，和/或由随机数发生器从存储表中随机地选择，并被馈送到用于创建要发送的波形的信号发生电路中。
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公开(公告)号：US20200350933A1
公开(公告)日：2020-11-05
申请号：US16403442
申请日：2019-05-03
Applicant: RAYTHEON COMPANY
Inventor： Harry B. Marr , Daniel Thompson , Aleksandr S. Radunsky
IPC: H04B1/04 , H04B1/03 , H04B10/516
Abstract: A transmitter. In some embodiments, the transmitter has an electrical input and an optical output. The transmitter may include a light source; an optical amplitude modulator having an optical input connected to the light source, a modulation input connected to the electrical input, and an output; and a first gated optical comparator, having a sampling clock input, an analog input connected to the output of the optical amplitude modulator, and an output. The first gated optical comparator may be configured to generate, for each cycle of an optical sampling clock signal received at the sampling clock input, a one-bit digital representation of an analog optical signal received at the analog input.
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公开(公告)号：US10698083B2
公开(公告)日：2020-06-30
申请号：US15686630
申请日：2017-08-25
Applicant: Raytheon Company
Inventor： Daniel Thompson , Harry B. Marr , Ian Robinson , Jeffrey Caldwell
Abstract: A system and method of digital beamforming for a monobit phased array radar system includes providing a plurality of monobit analog signals received by at least one antenna to at least one field programmable gate array (FPGA). A plurality of monobit SerDes transceivers within the FPGA convert the plurality of monobit analog signals into a plurality of multibit digital signals, each of the multibit digital signals being modified according to a digital signal conditioning value to calibrate, phase align, and synchronize the digital signals. A digital beam is formed by coherently combining the plurality of digital signals within the FPGA.
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公开(公告)号：US10348338B2
公开(公告)日：2019-07-09
申请号：US15287356
申请日：2016-10-06
Applicant: Raytheon Company
Inventor： Harry B. Marr , Mark J. Rosker , Justin Hodiak , Charles T. Hansen
Abstract: A signal identification system includes an analog adaptive channelizer having a plurality of channels. Each channel has a channel size defined by a bandwidth and a gain. The system further includes an electronic signal identification (ID) controller in signal communication with the analog adaptive channelizer. The ID controller is configured to determine a dynamic range event that modifies an energy level of an affected channel among the plurality of channels, and output a feedback signal including channel parameters based on the dynamic range event. The analog adaptive channelizer actively adjusts at least one of the bandwidth and the gain of the affected channel based on the feedback to change the channel size of the affected channel.
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公开(公告)号：US10320596B2
公开(公告)日：2019-06-11
申请号：US15721467
申请日：2017-09-29
Applicant: Raytheon Company
Inventor： Daniel Thompson , Harry B. Marr
IPC: H04B1/10 , H04B3/14 , H04B10/2507 , H04L27/12 , H04B7/005
Abstract: Circuit and method for modulating filter coefficients of a frequency channelizer having a filter bank include: receiving a wide spectrum input signal; modulating the filter coefficients of the filter bank to sweep a center frequency of each channel of the frequency channelizer, using a modulation scheme; and inputting frequency offset compensation caused by the modulation, and output signals of the frequency channelizer to an application processing circuit to convert the output signals to their original center frequencies.
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