公开(公告)号：US20210327864A1

公开(公告)日：2021-10-21

申请号：US16851357

申请日：2020-04-17

Applicant: QUALCOMM Incorporated

Inventor： Joan Rey Villarba BUOT ,  Zhijie WANG

IPC: H01L25/18 ,  H01L23/495 ,  H01L23/31 ,  H01L27/01 ,  H01L49/02 ,  H01L23/00 ,  H01G4/30 ,  H01L25/00

Abstract: Certain aspects of the present disclosure generally relate to a modular capacitor array, such as for an integrated circuit package, and methods for fabricating the same. One example integrated circuit package generally includes a package substrate, a semiconductor die disposed above the package substrate, and at least one modular capacitor array disposed below the package substrate. The modular capacitor array may be a pre-packaged array of capacitive elements, such as multi-layer ceramic capacitors (MLCCs).

公开(公告)号：US20210175178A1

公开(公告)日：2021-06-10

申请号：US16704378

申请日：2019-12-05

Applicant: QUALCOMM Incorporated

Inventor： Hong Bok WE ,  Aniket PATIL ,  Kuiwon KANG ,  Zhijie WANG

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56

Abstract: A package comprising a first integrated device, a first encapsulation layer, a redistribution portion, a second integrated device and an encapsulation layer. The first encapsulation layer encapsulates the first integrated device. The redistribution portion includes a plurality of redistribution interconnects. The redistribution portion includes a first surface and a second surface. The first integrated device and the first encapsulation layer are coupled to the first surface of the redistribution portion. The second integrated device is coupled to the second surface of the redistribution portion. The second encapsulation layer is coupled to the second surface of the redistribution portion such that the second encapsulation layer encapsulates the second integrated device.

公开(公告)号：US20250125234A1

公开(公告)日：2025-04-17

申请号：US18486970

申请日：2023-10-13

Applicant: QUALCOMM Incorporated

Inventor： Manuel ALDRETE ,  Rajneesh KUMAR ,  Zhijie WANG ,  Aniket PATIL ,  Srikanth KULKARNI

IPC: H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L25/10

Abstract: In an aspect, an integrated circuit (IC) package includes a base structure, an IC component disposed on the base structure, a plurality of interposer connection structures disposed on the base structure, and an interposer structure disposed over the IC component and the plurality of interposer connection structures. The plurality of interposer connection structures is configured to connect the base structure and the interposer structure. Each interposer connection structure of the plurality of interposer connection structures includes a bond ball portion that is connected to the base structure, and a bond wire portion that is coupled to the bond ball portion and extends toward the interposer structure. A width of the bond ball portion is greater than a width of the bond wire portion.

公开(公告)号：US20250046688A1

公开(公告)日：2025-02-06

申请号：US18363557

申请日：2023-08-01

Applicant: QUALCOMM Incorporated

Inventor： Zhijie WANG ,  Rajneesh KUMAR ,  Manuel ALDRETE ,  Sang-Jae LEE ,  Seongho KIM

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L25/10 ,  H10B80/00

Abstract: An integrated device includes a die including active circuitry and a first set of contacts; a first substrate including a second set of contacts and a third set of contacts on a first side of the first substrate and a fourth set of contacts on a second side of the first substrate; a mold compound disposed on the first side of the first substrate and at least partially encapsulating the die; and a set of through mold conductors coupled to the third set of contacts and extending through the mold compound, wherein an upper surface of the mold compound, an upper surface of the die, and an upper surface of each of the set of through mold conductors are coplanar.

公开(公告)号：US20220148952A1

公开(公告)日：2022-05-12

申请号：US17093954

申请日：2020-11-10

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Zhijie WANG ,  Joan Rey Villarba BUOT ,  Hong Bok WE

IPC: H01L23/498 ,  H01L25/10 ,  H01L23/495 ,  H01L25/00

Abstract: A device comprising a first package and a second package coupled to the first package. The first package includes a first substrate, at least one gradient interconnect structure coupled to the first substrate, and a first integrated device coupled to the first substrate. The second package includes a second substrate and a second integrated device coupled to the second substrate. The second substrate is coupled to the at least one gradient interconnect structure.

公开(公告)号：US20200381344A1

公开(公告)日：2020-12-03

申请号：US16424700

申请日：2019-05-29

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Hong Bok WE ,  Kuiwon KANG ,  Zhijie WANG

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/16 ,  H01L21/48 ,  H01L23/00

Abstract: Certain aspects of the present disclosure generally relate to a chip package having a split conductive pad for coupling to a device terminal. An example chip package generally includes a layer, a first plurality of conductive pads disposed on the layer, at least one conductive trace disposed on the layer and between the first plurality of conductive pads, and an electrical component having a first terminal coupled to the first plurality of conductive pads and disposed above the at least one conductive trace.

公开(公告)号：US20200350260A1

公开(公告)日：2020-11-05

申请号：US16400264

申请日：2019-05-01

Applicant: QUALCOMM Incorporated

Inventor： Aniket PATIL ,  Kuiwon KANG ,  Zhijie WANG ,  Ming YI

IPC: H01L23/552 ,  H01L23/04 ,  H01L21/52 ,  H01L23/498

Abstract: Certain aspects of the present disclosure provide an integrated circuit (IC) package and techniques for fabricating the IC package. The IC package generally includes a substrate, an IC disposed above the substrate, and a shielding layer coupled to a layer of the substrate, wherein the shielding layer is disposed above the substrate adjacent to the IC, and below an upper surface of the IC.

公开(公告)号：US20190393120A1

公开(公告)日：2019-12-26

申请号：US16016888

申请日：2018-06-25

Applicant: QUALCOMM Incorporated

Inventor： Kuiwon KANG ,  Zhijie WANG ,  Bohan YAN

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/498 ,  H01L23/00

Abstract: An integrated circuit package having an interposer with increased thermal conductivity and techniques for fabricating such an integrated circuit package are provided. One example integrated circuit package generally includes a package substrate, at least one semiconductor die disposed above the package substrate, and an interposer disposed above the at least one semiconductor die. The interposer includes a dielectric layer, and a metallic plate disposed adjacent to a first portion of the dielectric layer. The height of the metallic plate is greater than a height of the dielectric layer.