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    RADIO-FREQUENCY INTEGRATED CIRCUITS (RFICS) INCLUDING A POROSIFIED SEMICONDUCTOR ISOLATION REGION TO REDUCE NOISE INTERFERENCE AND RELATED FABRICATION METHODS
    22.
    发明申请
    RADIO-FREQUENCY INTEGRATED CIRCUITS (RFICS) INCLUDING A POROSIFIED SEMICONDUCTOR ISOLATION REGION TO REDUCE NOISE INTERFERENCE AND RELATED FABRICATION METHODS 有权

    公开(公告)号：US20230088569A1

    公开(公告)日：2023-03-23

    申请号：US17482733

    申请日：2021-09-23

    Applicant: QUALCOMM Incorporated

    Inventor： Ranadeep Dutta ,  Jonghae Kim ,  Je-Hsiung Lan

    IPC: H01L27/12 ,  H01L23/66 ,  H01L21/762 ,  H01L21/84

    Abstract: Radio frequency (RF) circuits generate noise that can interfere with other RF circuits on the same semiconductor die. An isolation material disposed in an isolation region between a first active region of a first RF circuit and a second active region of a second RF circuit comprises a porosified region of the semiconductor material of the semiconductor die. The isolation material (e.g., porosified material) has a higher resistivity and lower permittivity than the semiconductor material to reduce transmission of noise interference between the first RF circuit and the second RF circuit. The isolation material in the isolation region of the semiconductor material comprises a porosity in the range 20% to 50% higher than the porosity of the semiconductor material in the first and second active regions. The porosified region has a lower permittivity and a higher resistivity than the non-porosified region to protect against the transmission of noise interference.

    Three-dimensional (3D) integrated circuit with passive elements formed by hybrid bonding
    23.
    发明授权
    Three-dimensional (3D) integrated circuit with passive elements formed by hybrid bonding 有权

    公开(公告)号：US11605620B2

    公开(公告)日：2023-03-14

    申请号：US16906509

    申请日：2020-06-19

    Applicant: QUALCOMM Incorporated

    Inventor： Je-Hsiung Lan ,  Ranadeep Dutta ,  Jonghae Kim

    IPC: H01L25/16 ,  H01L23/00 ,  H01L49/02 ,  H01L27/092 ,  H03H9/17

    Abstract: A three-dimensional integrated circuit (3DIC) and techniques for fabricating a 3DIC. An example semiconductor device generally includes an integrated circuit (IC) having a first plurality of pads coupled to components of the IC, wherein a first oxide material is disposed between the first plurality of pads, and a second plurality of pads, wherein at least a portion of the first plurality of pads is bonded to at least a portion of the second plurality of pads, and wherein a second oxide material is disposed between the second plurality of pads and is bonded to the first oxide material b. The semiconductor device may also include a substrate disposed above the second plurality of pads, one or more passive devices adjacent to the substrate, and one or more vias formed through the substrate, wherein at least one of the second plurality of pads is coupled to the one or more vias.

    SURFACE ACOUSTIC WAVE (SAW) FILTER PACKAGES EMPLOYING AN ENHANCED THERMALLY CONDUCTIVE CAVITY FRAME FOR HEAT DISSIPATION, AND RELATED FABRICATION METHODS
    24.
    发明申请
    SURFACE ACOUSTIC WAVE (SAW) FILTER PACKAGES EMPLOYING AN ENHANCED THERMALLY CONDUCTIVE CAVITY FRAME FOR HEAT DISSIPATION, AND RELATED FABRICATION METHODS 有权

    公开(公告)号：US20230054636A1

    公开(公告)日：2023-02-23

    申请号：US17409282

    申请日：2021-08-23

    Applicant: QUALCOMM Incorporated

    Inventor： Ranadeep Dutta ,  Jonghae Kim ,  Je-Hsiung Lan

    IPC: H03H9/64 ,  H03H3/10 ,  H03H9/10 ,  H03H9/05 ,  H03H9/02

    Abstract: Surface acoustic wave (SAW) filter packages employing an enhanced thermally conductive cavity frame for heat dissipation, and related fabrication methods are disclosed. The SAW filter package also includes a cavity frame comprising a perimeter structure and a cavity inside the perimeter structure coupled to a substrate of a piezoelectric material that contains interdigital transducers (IDTs). A cap substrate is disposed on the perimeter structure of the cavity frame to enclose an air cavity inside the perimeter structure between a substrate and the cap substrate. In exemplary aspects, to effectively dissipate heat generated in the SAW filter package to maintain the desired performance of the SAW filter, the cavity frame is comprised of a material that has an enhanced thermal conductivity. The heat generated in the SAW filter package can more effectively be dissipated, particularly at edges and corners of the cavity frame where hot spots can particularly occur.

    THREE TERMINAL SEMICONDUCTOR DEVICE WITH VARIABLE CAPACITANCE
    25.
    发明申请
    THREE TERMINAL SEMICONDUCTOR DEVICE WITH VARIABLE CAPACITANCE 审中-公开
    具有可变电容的三端子半导体器件

    公开(公告)号：US20140232451A1

    公开(公告)日：2014-08-21

    申请号：US13770005

    申请日：2013-02-19

    Applicant: QUALCOMM INCORPORATED

    Inventor： Ranadeep Dutta

    IPC: H01L29/93 ,  G05B99/00

    CPC classification number: H01L29/93 ,  H01L27/0808 ,  H01L29/66174 ,  H01L29/66181 ,  H01L29/945

    Abstract: Methods and apparatus for implementing variable, e.g., tunable, 3 terminal capacitance devices are described. In various embodiments vertical control pillars spaced apart from one another extend in a well having an opposite polarity than the polarity of the control pillars. The control pillars are arranged in a line that extends parallel to but between a deep trench gate and a well pickup. By varying the voltage applied to the control pillars the size of the depletion zone around the pillars can be varied resulting in a change in capacitance between the trench gate and pickup terminal connected to the well pickup. The generally vertical nature of the control pillars facilities control over a wide range of voltages while allowing for manufacturing using common semiconductor manufacturing steps making the device easy to implement on a chip with other semiconductor devices.

    Abstract translation: 描述了实现可变的，例如可调谐的3端子电容器件的方法和装置。 在各种实施例中，彼此间隔开的垂直控制柱在具有与控制柱的极性相反的极性的井中延伸。 控制柱布置成平行于深沟槽栅极和阱拾取器之间延伸的线。 通过改变施加到控制柱的电压，可以改变柱周围的耗尽区的尺寸，导致沟槽栅极和连接到阱拾取器的拾取端之间的电容变化。 控制支柱设施的大体上垂直的特性控制在宽范围的电压，同时允许使用通用的半导体制造步骤的制造，使得器件易于与其他半导体器件在芯片上实现。

    DEVICES INCLUDING THROUGH-SUBSTRATE VIAS (TSVs) FOR BACKSIDE INTERCONNECTION, AND RELATED FABRICATION METHODS
    26.
    发明申请
    DEVICES INCLUDING THROUGH-SUBSTRATE VIAS (TSVs) FOR BACKSIDE INTERCONNECTION, AND RELATED FABRICATION METHODS 有权

    公开(公告)号：US20240421790A1

    公开(公告)日：2024-12-19

    申请号：US18336305

    申请日：2023-06-16

    Applicant: QUALCOMM Incorporated

    Inventor： Je-Hsiung Lan ,  Jonghae Kim ,  Ranadeep Dutta

    IPC: H03H3/08 ,  H03H9/02 ,  H03H9/64

    Abstract: A package includes a device that includes electrodes disposed on a piezoelectric layer on a first, front side of a first substrate and vertical interconnect accesses (vias) that extend through the substrate to couple the electrodes to a second, back side of the first substrate. The vias may be through-substrate vias (TSVs). Employing a first substrate (e.g., silicon) in which vias can be formed, the electrodes on the front side can be coupled to interconnects on the back side to minimize electrical path distances to and from the device for a higher a Q factor. Also, a capacitor may be formed on a second, back side of the substrate and coupled to an electrode of the device by a via rather than having an electrical path from a first substrate, to an external capacitor on a package substrate. A thermal conductive path is also reduced for improved heat dissipation.

    Reducing Parasitic Capacitance
    27.
    发明公开
    Reducing Parasitic Capacitance 审中-公开

    公开(公告)号：US20240097619A1

    公开(公告)日：2024-03-21

    申请号：US17932403

    申请日：2022-09-15

    Applicant: QUALCOMM Incorporated

    Inventor： Ranadeep Dutta ,  Abdellatif Bellaouar ,  Chuan-Cheng Cheng

    IPC: H03F1/26 ,  H03F3/45

    CPC classification number: H03F1/26 ,  H03F3/45475 ,  H03F2200/372

    Abstract: An apparatus is disclosed for reducing parasitic capacitance. In an example aspect, an apparatus includes an amplifier having a differential cascode configuration. Each stack of the amplifier includes a first transistor configured to operate as an input stage and a second transistor configured to operate as a cascode stage. The first and second transistors each include two channel terminal regions having a doping type that is uniform across the two channel terminal regions. Surfaces of first channel terminal regions of the first and second transistors abut a first and second quantity of electrical contacts, respectively. Second channel terminal regions of the first and second transistors form a floating region at a floating node. Each of the first quantity of electrical contacts and the second quantity of electrical contacts is greater than a third quantity of electrical contacts abutting a surface of the floating region.

    SURFACE ACOUSTIC WAVE (SAW) DEVICES WITH A DIAMOND BRIDGE ENCLOSED WAVE PROPAGATION CAVITY
    29.
    发明申请
    SURFACE ACOUSTIC WAVE (SAW) DEVICES WITH A DIAMOND BRIDGE ENCLOSED WAVE PROPAGATION CAVITY 有权

    公开(公告)号：US20220231660A1

    公开(公告)日：2022-07-21

    申请号：US17153520

    申请日：2021-01-20

    Applicant: QUALCOMM Incorporated

    Inventor： Ranadeep Dutta ,  Jonghae Kim ,  Je-Hsiung Lan

    IPC: H03H9/02 ,  H03H9/145 ,  H03H3/08

    Abstract: A surface acoustic wave (SAW) device includes a first interdigital transducer (IDT) and a second IDT each including interdigital electrodes disposed on a first surface of a substrate of piezoelectric material. The SAW device includes a diamond bridge enclosing an air cavity over a wave propagation region on the first surface of the substrate. The diamond bridge has a reduced height and provides improved thermal conductivity to avoid a reduction in performance and/or life span caused by heat generated in the SAW device. A process of fabricating a SAW device includes forming the first IDT and the second IDT in a metal layer on a first surface of a substrate comprising a piezoelectric material, the first IDT and the second IDT disposed in a wave propagation region of the first surface of the substrate, and forming a diamond bridge disposed above the wave propagation region.

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