公开(公告)号：US20240097619A1

公开(公告)日：2024-03-21

申请号：US17932403

申请日：2022-09-15

Applicant: QUALCOMM Incorporated

Inventor： Ranadeep Dutta ,  Abdellatif Bellaouar ,  Chuan-Cheng Cheng

IPC: H03F1/26 ,  H03F3/45

CPC classification number: H03F1/26 ,  H03F3/45475 ,  H03F2200/372

Abstract: An apparatus is disclosed for reducing parasitic capacitance. In an example aspect, an apparatus includes an amplifier having a differential cascode configuration. Each stack of the amplifier includes a first transistor configured to operate as an input stage and a second transistor configured to operate as a cascode stage. The first and second transistors each include two channel terminal regions having a doping type that is uniform across the two channel terminal regions. Surfaces of first channel terminal regions of the first and second transistors abut a first and second quantity of electrical contacts, respectively. Second channel terminal regions of the first and second transistors form a floating region at a floating node. Each of the first quantity of electrical contacts and the second quantity of electrical contacts is greater than a third quantity of electrical contacts abutting a surface of the floating region.