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    In-field monitoring of on-chip thermal, power distribution network, and power grid reliability
    21.
    发明授权
    In-field monitoring of on-chip thermal, power distribution network, and power grid reliability 有权

    公开(公告)号：US11416049B2

    公开(公告)日：2022-08-16

    申请号：US16826729

    申请日：2020-03-23

    Applicant: QUALCOMM Incorporated

    Inventor： Palkesh Jain ,  Rahul Gulati

    IPC: G01R31/317 ,  G06F1/20 ,  G06F1/3203

    Abstract: Various embodiments may include methods and systems for monitoring characteristics of a system-on-a-chip. Various embodiments may include inputting, from a test data input connection, test data to a first scan chain section including a first group of logic gates located within a first region of the SoC. Various embodiments may include providing, from a first clock gate associated with the first region of the SoC, a clock signal to the first group of logic gates. Various embodiments may include measuring, using a first sensor, the characteristics at a second region of the SoC in response to providing the clock signal to the first group of logic gates. Embodiments may further include processing or analyzing measured characteristics to determine a testing result.

    On-chip frequency monitoring
    23.
    发明授权
    On-chip frequency monitoring 有权

    公开(公告)号：US10514401B2

    公开(公告)日：2019-12-24

    申请号：US15667116

    申请日：2017-08-02

    Applicant: QUALCOMM Incorporated

    Inventor： Bipin Duggal ,  Rahul Gulati ,  Sina Dena

    IPC: G01R23/02 ,  G01R31/317 ,  G01R23/10 ,  G01R23/15 ,  G01R35/00 ,  G01R23/14 ,  G01R23/00

    Abstract: In certain aspects of the disclosure, a frequency monitor includes a counter configured to receive a monitored clock signal, to count a number of periods of the monitored clock signal over a predetermined time duration, and to output a count value corresponding to the number of periods of the monitored clock signal. The frequency monitor also includes a comparator configured to receive the count value from the counter, to receive an expected count value, to compare the count value from the counter with the expected count value, and to output a pass status signal or a fail status signal based on the comparison.

    MEMORY ADDRESS FLIPPING TO DETERMINE DATA CONTENT INTEGRITY IN GPU SUB-SYSTEM
    28.
    发明申请
    MEMORY ADDRESS FLIPPING TO DETERMINE DATA CONTENT INTEGRITY IN GPU SUB-SYSTEM 审中-公开

    公开(公告)号：US20190139263A1

    公开(公告)日：2019-05-09

    申请号：US15804707

    申请日：2017-11-06

    Applicant: QUALCOMM Incorporated

    Inventor： Andrew Evan Gruber ,  Rahul Gulati ,  Brendon Lewis Johnson ,  Jay Chunsup Yun ,  Alex Kwang Ho Jong ,  Donghyun Kim

    IPC: G06T7/00 ,  G06K9/00 ,  G08G1/16 ,  B60R1/00

    Abstract: Techniques of this disclosure may include processing data using one or more processors to produce a first image, including storing intermediate first results of processing the data in at least one internal memory of the one or more processors according to a first memory access pattern, processing the data using the one or more processors to produce a second image, including storing intermediate second results of processing the data in the at least one internal memory of the one or more processors according to a second memory access pattern, wherein the second memory access pattern is different than the first memory access pattern, comparing the first image to the second image, and generating an interrupt if the comparison indicates that the first image is different than the second image.

    System and method for false pass detection in lockstep dual core or triple modular redundancy (TMR) systems
    29.
    发明授权
    System and method for false pass detection in lockstep dual core or triple modular redundancy (TMR) systems 有权

    公开(公告)号：US10089194B2

    公开(公告)日：2018-10-02

    申请号：US15176745

    申请日：2016-06-08

    Applicant: QUALCOMM Incorporated

    Inventor： Palkesh Jain ,  Virendra Bansal ,  Rahul Gulati

    IPC: G06F11/00 ,  G06F11/16 ,  G06F11/18

    Abstract: The disclosure relates to an apparatus and method for false pass detection in lockstep dual processing core systems, triple modular redundancy (TMR) systems, or other redundant processing systems. A false pass occurs when two processing cores generate matching data outputs, both of which are in error. A false pass may occur when the processing core are both subjected to substantially the same adverse condition, such as a supply voltage drop or a sudden temperature change or gradient. The apparatus includes processing cores configured to generate first and second data outputs and first and second timing violation signals. A voter-comparator validates the first and second data outputs if they match and the first and second timing violation signals indicate no timing violations. Otherwise, the voter comparator invalidates the first and second data outputs. Validated data outputs are used for performing additional operations, and invalidated data outputs may be discarded.

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