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    MEMORY WITH SYSTEM ECC
    21.
    发明申请
    MEMORY WITH SYSTEM ECC 有权

    公开(公告)号：US20210064463A1

    公开(公告)日：2021-03-04

    申请号：US16944110

    申请日：2020-07-30

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon SUH ,  Michael Hawjing LO ,  Dexter Tamio CHUN ,  Xavier Loic LELOUP ,  Laurent Rene MOLL

    IPC: G06F11/10 ,  G06F3/06

    Abstract: Methods and apparatuses for a system error-correcting code function are presented. The apparatus includes a memory configured to communicate with a host. The memory includes a memory array configured to store data. The memory is configured to provide the data stored in the memory array to the host in performing computing functions and configured to provide an error-correction code (ECC) associated with the data to the host. The ECC is not stored in the memory array in a first configuration of the memory and is stored in the memory array in a second configuration of the memory.

    ENHANCED DATA CLOCK OPERATIONS IN MEMORY
    22.
    发明申请
    ENHANCED DATA CLOCK OPERATIONS IN MEMORY 审中-公开

    公开(公告)号：US20200278802A1

    公开(公告)日：2020-09-03

    申请号：US16803977

    申请日：2020-02-27

    Applicant: Qualcomm Incorporated

    Inventor： Jungwon SUH ,  Dexter Tamio Chun ,  Michael Hawjing Lo ,  Shyamkumar Thoziyoor ,  Ravindra Kumar

    IPC: G06F3/06 ,  G06F12/0875

    Abstract: Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.

    DYNAMIC LINK ERROR PROTECTION IN MEMORY SYSTEMS
    23.
    发明申请
    DYNAMIC LINK ERROR PROTECTION IN MEMORY SYSTEMS 审中-公开

    公开(公告)号：US20190324850A1

    公开(公告)日：2019-10-24

    申请号：US16503368

    申请日：2019-07-03

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon SUH ,  Alain ARTIERI ,  Dexter Tamio CHUN ,  Deepti Vijayalakshmi SRIRAMAGIRI

    IPC: G06F11/10 ,  G06F3/06

    Abstract: Errors can be introduced when data is transferred over a link between two entities such as between a host and a memory. Link error protection schemes can be implemented to detect and correct errors that occur on the link to enhance transmission reliability. However, these benefits are not without costs since such protection schemes increase both latency and power consumption. In one or more aspects, it is proposed to dynamically adjust the level of link error protection applied to match any change in the operating environment. For example, likelihood of link errors strongly correlates with the link speed. If the link speed is increased, a greater level of link error protection can be applied to counteract the increase in the link errors. If the link speed is decreased, the level of protection can be decreased so that latency and power consumption penalties can be minimized.

    PARTIAL REFRESH TECHNIQUE TO SAVE MEMORY REFRESH POWER
    27.
    发明申请
    PARTIAL REFRESH TECHNIQUE TO SAVE MEMORY REFRESH POWER 审中-公开

    公开(公告)号：US20200321051A1

    公开(公告)日：2020-10-08

    申请号：US16907103

    申请日：2020-06-19

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon SUH ,  Yanru LI ,  Michael Hawjing LO ,  Dexter Tamio CHUN

    IPC: G11C11/406 ,  G11C7/10

    Abstract: In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

    LINK ERROR CORRECTION IN MEMORY SYSTEM
    29.
    发明申请
    LINK ERROR CORRECTION IN MEMORY SYSTEM 审中-公开

    公开(公告)号：US20180060171A1

    公开(公告)日：2018-03-01

    申请号：US15643455

    申请日：2017-07-06

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon SUH

    IPC: G06F11/10 ,  G06F3/06

    CPC classification number: G06F11/1076 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0673 ,  G06F11/10 ,  G06F11/1048 ,  H03M13/31

    Abstract: Conventional link error correction techniques in memory subsystems include either widening the I/O width or increasing the burst length. However, both techniques have drawbacks. In one or more aspects, it is proposed to incorporate link error correction in both the host and the memory devices to address the drawbacks associated with the conventional techniques. The proposed memory subsystem is advantageous in that the interface architecture of conventional memory systems can be maintained. Also, the link error correction is capability is provided with the proposed memory subsystem without increasing the I/O width and without increasing the burst length.

    MEMORY ARRAY AND LINK ERROR CORRECTION IN A LOW POWER MEMORY SUB-SYSTEM
    30.
    发明申请
    MEMORY ARRAY AND LINK ERROR CORRECTION IN A LOW POWER MEMORY SUB-SYSTEM 审中-公开
    低功耗存储器子系统中的存储器阵列和链路错误校正

    公开(公告)号：US20170004035A1

    公开(公告)日：2017-01-05

    申请号：US14859063

    申请日：2015-09-18

    Applicant: QUALCOMM Incorporated

    Inventor： Jungwon SUH ,  David Ian WEST

    IPC: G06F11/10 ,  G11C29/52

    CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C29/52

    Abstract: A method of memory array and link error correction in a low power memory sub-system includes embedding error correction code (ECC) parity bits within unused data mask bits during a normal write operation and during a read operation. The method also includes embedding the ECC parity bits in a mask write data byte corresponding to an asserted data mask bit during a mask write operation.

    Abstract translation: 在低功率存储器子系统中的存储器阵列和链路纠错的方法包括在正常写入操作期间和在读取操作期间嵌入未使用的数据屏蔽位内的纠错码（ECC）奇偶校验位。 该方法还包括在掩模写入操作期间将ECC奇偶校验位嵌入对应于断言的数据屏蔽位的掩码写数据字节。

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