公开(公告)号：US09325341B2

公开(公告)日：2016-04-26

申请号：US14475852

申请日：2014-09-03

Applicant: QUALCOMM Incorporated

Inventor： Elias Hani Dagher ,  Kentaro Yamamoto ,  Dinesh Jagannath Alladi

IPC: H03M3/00 ,  H03M1/34

CPC classification number: H03M1/34 ,  H03M3/30 ,  H03M3/37 ,  H03M3/426 ,  H03M3/454 ,  H03M3/458 ,  H03M3/464

Abstract: In one embodiment, a circuit includes a quantizer configured to convert an analog input signal to a digital signal. The quantizer includes a first feedback path including a first digital to analog converter (DAC) coupled from an output of the quantizer to a summing junction that is coupled to an input of the quantizer. The first feedback path converts the digital signal to a first corresponding analog value for combining with the analog input signal at the summing junction. Also, the quantizer includes a plurality of excess loop delay (ELD) compensation paths coupled to the summing junction configured to compensate for excess loop delay from a second feedback path coupled from the output of the quantizer to input of the quantizer via a loop filter. Second DACs in the second feedback path convert the digital signal to a second corresponding analog value for combining with the analog input signal.

Abstract translation: 在一个实施例中，电路包括被配置为将模拟输入信号转换成数字信号的量化器。 量化器包括第一反馈路径，其包括从量化器的输出耦合到耦合到量化器的输入的求和结点的第一数模转换器（DAC）。 第一反馈路径将数字信号转换为第一对应的模拟值，以与求和点处的模拟输入信号组合。 此外，量化器还包括耦合到求和点的多个过剩环路延迟（ELD）补偿路径，其被配置为补偿从量化器的输出耦合到从量化器经由环路滤波器输入的第二反馈路径的过多的环路延迟。 第二反馈路径中的第二DAC将数字信号转换为第二对应的模拟值，以与模拟输入信号组合。

公开(公告)号：US11770129B2

公开(公告)日：2023-09-26

申请号：US17484581

申请日：2021-09-24

Applicant: Qualcomm Incorporated

Inventor： Seyed Arash Mirhaj ,  Lei Sun ,  Yuhua Guo ,  Elias Dagher ,  Aram Akhavan ,  Yan Wang ,  Dinesh Jagannath Alladi

IPC: H03M1/06 ,  H03M1/16 ,  H03M1/38 ,  H04B1/40

CPC classification number: H03M1/167 ,  H03M1/38 ,  H04B1/40

Abstract: An apparatus is disclosed for pipelined analog-to-digital conversion. In an example aspect, the apparatus includes a pipelined analog-to-digital converter (ADC). The pipelined ADC includes a first stage and a second stage. The first stage includes a sampler and a quantizer coupled to the sampler. The first stage also includes a current distribution circuit coupled to the sampler. The second stage includes a sampler coupled to the current distribution circuit and a quantizer coupled to the sampler of the second stage.

公开(公告)号：US11546004B2

公开(公告)日：2023-01-03

申请号：US17211769

申请日：2021-03-24

Applicant: QUALCOMM Incorporated

Inventor： Meysam Azin ,  Li Lu ,  Anees Habib ,  Chinmaya Mishra ,  Damin Cao ,  Arul Balasubramaniyan ,  David Ta-hsiang Lin ,  Shuang Zhu ,  Dinesh Jagannath Alladi

IPC: H04B1/04 ,  H03M3/00 ,  H03M1/46

Abstract: Aspects of the disclosure relate to an apparatus for wireless communication. The apparatus may include a set of power detectors configured to generate a set of analog signals related to a set of output signal power levels of a set of transmit chains of a transmitter, respectively; an analog summer; a set of switching devices configured to send a selected one or more of the set of analog signals to the analog summer, and substantially isolated unselected one or more of the set of power detectors from the analog summer, wherein the analog summer is configured to generate a cumulative analog signal based on a sum of the selected one or more of the set of analog signals; an analog-to-digital converter (ADC) configured to generate a digital signal based on the cumulative analog signal; and a controller configured to control the set of switching devices.

公开(公告)号：US10651864B2

公开(公告)日：2020-05-12

申请号：US15962967

申请日：2018-04-25

Applicant: QUALCOMM Incorporated

Inventor： Timothy Donald Gathman ,  Yuhua Guo ,  Lai Kan Leung ,  Elias Dagher ,  Dinesh Jagannath Alladi

IPC: H03M1/00 ,  H03M1/12 ,  H04B1/16 ,  H03F3/45 ,  H03F3/19 ,  H03F3/24 ,  H03M1/52 ,  G04F5/00 ,  H03M1/54 ,  G11C27/02

Abstract: A receiver may include a time-interleaved charge sampler comprising a charge sampler switch in series with a charge sampler capacitor. The receiver may also include a current buffer configured to drive the time-interleaved charge sampler.

公开(公告)号：US10439627B2

公开(公告)日：2019-10-08

申请号：US16010117

申请日：2018-06-15

Applicant: Qualcomm Incorporated

Inventor： Sean Baker ,  Dinesh Jagannath Alladi ,  Balasubramanian Sivakumar ,  Kentaro Yamamoto

IPC: H03M1/06 ,  H03M1/00 ,  H04B1/3827

Abstract: An example apparatus is disclosed for alias rejection through charge sharing. The apparatus includes a filter-sampling network, a digital-to-analog converter, and a charge-sharing switch. The filter-sampling network includes a capacitor and a first switch, which is coupled between an input node and the capacitor. The filter-sampling network is configured to connect or disconnect the capacitor to or from the input node via the first switch. The digital-to-analog converter includes a capacitor array and a second switch, which is coupled between the input node and the capacitor array. The capacitor array is coupled between the second switch and a charge-sharing node. The digital-to-analog converter is configured to connect or disconnect the capacitor array to or from the input node via the second switch. The charge-sharing switch is coupled between the charge-sharing node and the capacitor and is configured to connect or disconnect the capacitor to or from the digital-to-analog converter.

公开(公告)号：US20190190529A1

公开(公告)日：2019-06-20

申请号：US16010117

申请日：2018-06-15

Applicant: Qualcomm Incorporated

Inventor： Sean Baker ,  Dinesh Jagannath Alladi ,  Balasubramanian Sivakumar ,  Kentaro Yamamoto

IPC: H03M1/06 ,  H03M1/00

CPC classification number: H03M1/0629 ,  H03M1/002 ,  H03M1/468 ,  H04B1/3827

Abstract: An example apparatus is disclosed for alias rejection through charge sharing. The apparatus includes a filter-sampling network, a digital-to-analog converter, and a charge-sharing switch. The filter-sampling network includes a capacitor and a first switch, which is coupled between an input node and the capacitor. The filter-sampling network is configured to connect or disconnect the capacitor to or from the input node via the first switch. The digital-to-analog converter includes a capacitor array and a second switch, which is coupled between the input node and the capacitor array. The capacitor array is coupled between the second switch and a charge-sharing node. The digital-to-analog converter is configured to connect or disconnect the capacitor array to or from the input node via the second switch. The charge-sharing switch is coupled between the charge-sharing node and the capacitor and is configured to connect or disconnect the capacitor to or from the digital-to-analog converter.

公开(公告)号：US10243578B2

公开(公告)日：2019-03-26

申请号：US15440612

申请日：2017-02-23

Applicant: QUALCOMM Incorporated

Inventor： Elias Dagher ,  Yan Wang ,  Mohammad Meysam Zargham ,  Dinesh Jagannath Alladi

IPC: H03M3/00 ,  H03M1/12

Abstract: Certain aspects of the present disclosure provide methods and apparatus for implementing sampling rate scaling of an excess loop delay (ELD)-compensated continuous-time delta-sigma modulator (CTDSM) analog-to-digital converter (ADC). One example ADC generally includes a loop filter; a quantizer having an input coupled to an output of the loop filter; one or more digital-to-analog converters (DACs), each having an input coupled to an output of the quantizer, an output coupled to an input of the loop filter, and a data latch comprising a clock input for the DAC coupled to a clock input for the ADC; and a clock delay circuit having an input coupled to the clock input for the ADC and an output coupled to a clock input for the quantizer.

公开(公告)号：US20160056833A1

公开(公告)日：2016-02-25

申请号：US14465650

申请日：2014-08-21

Applicant: QUALCOMM Incorporated

Inventor： Seyed Arash Mirhaj ,  Sameer Wadhwa ,  Dinesh Jagannath Alladi ,  Kentaro Yamamoto ,  Xiaoke Wen ,  Masoud Ensafdaran ,  Weihua Chen

IPC: H03M1/72

CPC classification number: H03M1/72 ,  H03M1/0612 ,  H03M1/66 ,  H03M1/804 ,  H03M1/806

Abstract: Reducing signal dependence for a reference voltage of a CDAC includes: splitting a decoupling capacitor into a plurality of capacitors smaller in size than a size of the decoupling capacitor; isolating at least one of the plurality of capacitors from a sampling buffer coupled to the reference voltage during a conversion phase; and supplying an appropriate amount of charge needed to replenish charge drawn by capacitors in the CDAC at each conversion step using a charge pump to pump in a dummy charge to the CDAC so that resulting configurations of the CDAC draw substantially similar amount of charge for each code change of the each conversion step.

Abstract translation: 降低对CDAC的参考电压的信号依赖性包括：将去耦电容器分成尺寸小于去耦电容器的尺寸的多个电容器; 在转换阶段期间将耦合到参考电压的采样缓冲器中的至少一个电容器隔离; 并且在每个转换步骤中使用电荷泵提供在CDAC中由电容器吸收的电荷所需的适当量的电荷，以将虚拟电荷泵送到CDAC，使得CDAC的所得结构为每个代码绘制基本相似的电荷量 更改每个转换步骤。