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21.发明授权公开(公告)号：US10833898B2
公开(公告)日：2020-11-10
申请号：US15857891
申请日：2017-12-29
Applicant: Oracle International Corporation
Inventor： Kunmo Kim , Rajesh Kumar , Dawei Huang , Frankie Liu , Suwen Yang
Abstract: A method and apparatus for correcting baseline wander is disclosed. The method and apparatus may include generating filtered signals by filtering input signals using a filter circuit. An equalizer circuit using the filtered signals may generate output signals. Feedback networks may be configured to couple a respective output signal to a corresponding filtered signal.
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公开(公告)号：US10483952B1
公开(公告)日：2019-11-19
申请号：US15971126
申请日：2018-05-04
Applicant: Oracle International Corporation
Inventor： Jianghui Su , Xun Zhang , Muthukumar Vairavan , Rajesh Kumar , Dawei Huang
Abstract: A method and an apparatus for correcting baseline wander is disclosed. The method and apparatus may include receiving a serial data stream that encodes a plurality of data symbols, and determining an average magnitude of a first data value included in one or more data symbols of a subset of the plurality of data symbols, and an average magnitude of a second value included in the one of more data symbols of the subset of the plurality of data symbols. A common mode operating point of an equalizer circuit may be adjusted using the average magnitude of the first data value and the average magnitude of the second data value.
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公开(公告)号：US20190341914A1
公开(公告)日：2019-11-07
申请号：US15971126
申请日：2018-05-04
Applicant: Oracle International Corporation
Inventor： Jianghui Su , Xun Zhang , Muthukumar Vairavan , Rajesh Kumar , Dawei Huang
Abstract: A method and an apparatus for correcting baseline wander is disclosed. The method and apparatus may include receiving a serial data stream that encodes a plurality of data symbols, and determining an average magnitude of a first data value included in one or more data symbols of a subset of the plurality of data symbols, and an average magnitude of a second value included in the one of more data symbols of the subset of the plurality of data symbols. A common mode operating point of an equalizer circuit may be adjusted using the average magnitude of the first data value and the average magnitude of the second data value.
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公开(公告)号：US10348535B1
公开(公告)日：2019-07-09
申请号：US15954072
申请日：2018-04-16
Applicant: Oracle International Corporation
Inventor： Rajesh Kumar , Seno Judaprawira , Dawei Huang
Abstract: A reference generator for use with serial link data communication is disclosed. Broadly speaking, a decision circuit may perform a comparison between a particular data symbol included in a serial data stream and a difference between a voltage level of a first signal and a voltage level of a second signal, and generate an output data value based on a result of the comparison. A reference generator circuit may selectively sink a first current value from either the first signal or the second signal based upon another output data value generated from another data symbol included in the serial data stream that was to received prior to the particular data symbol.
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公开(公告)号：US10142089B2
公开(公告)日：2018-11-27
申请号：US15466469
申请日：2017-03-22
Applicant: Oracle International Corporation
Inventor： Yuhan Yao , Xun Zhang , Dawei Huang , Jianghui Su , Muthukumar Vairavan , Chaitanya Palusa
Abstract: Embodiments include systems and methods for improving link performance and tracking capability of a baud-rate clock data recovery (CDR) system using transition pattern detection. For example, a multi-level signal is received via a data channel and converted to a pseudo-NRZ signal. CDR early/late voting can be derived from the converted (baud-rate) pseudo-NRZ signal and from error signals from the received PAM4 signal, and the voting can be implemented with different phase error detector (PED) functional approaches. Different approaches can yield different CDR performance characteristics and can tend to favor different PAM4 transition patterns. Embodiments can identify jittery patterns for a particular CDR implementation and can add features to the CDR to filter out those patterns from being used for CDR early/late voting.
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Patent Agency Ranking
公开(公告)号：US20180278406A1
公开(公告)日：2018-09-27
申请号：US15464972
申请日：2017-03-21
Applicant: Oracle International Corporation
Inventor： Chaitanya Palusa , Dawei Huang , Jiangyuan Li , Pradeep Nagarajan
IPC: H04L7/00
Abstract: Embodiments enable built-in sinusoidal jitter injection, for example, in a serializer/deserializer (SERDES) circuit. For example, embodiments can receive a tracking profile that corresponds to a predetermined sinusoidal jitter (SJ) profile and a predetermined phase interpolator (PI) profile. A shift determination can be made for each of a plurality of insertion times according to the tracking profile, the shift determination indicating whether to adjust phase interpolation of the SERDES circuit. At each of the plurality of insertion times, a phase adjustment signal can be generated as a function of the shift determination. For example, the phase adjustment signal can indicate a control code for a phase interpolator coupled to a clock generator of the SERDES, and the signal can be output to the phase interpolator. Some implementations adjust the phase interpolator in response to the phase adjustment signal, such that the phase interpolator injects SJ that substantially tracks the SJ profile.
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公开(公告)号：US10084591B1
公开(公告)日：2018-09-25
申请号：US15464972
申请日：2017-03-21
Applicant: Oracle International Corporation
Inventor： Chaitanya Palusa , Dawei Huang , Jiangyuan Li , Pradeep Nagarajan
IPC: H04L7/00
Abstract: Embodiments enable built-in sinusoidal jitter injection, for example, in a serializer/deserializer (SERDES) circuit. For example, embodiments can receive a tracking profile that corresponds to a predetermined sinusoidal jitter (SJ) profile and a predetermined phase interpolator (PI) profile. A shift determination can be made for each of a plurality of insertion times according to the tracking profile, the shift determination indicating whether to adjust phase interpolation of the SERDES circuit. At each of the plurality of insertion times, a phase adjustment signal can be generated as a function of the shift determination. For example, the phase adjustment signal can indicate a control code for a phase interpolator coupled to a clock generator of the SERDES, and the signal can be output to the phase interpolator. Some implementations adjust the phase interpolator in response to the phase adjustment signal, such that the phase interpolator injects SJ that substantially tracks the SJ profile.
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公开(公告)号：US11784855B2
公开(公告)日：2023-10-10
申请号：US18154248
申请日：2023-01-13
Applicant: Oracle International Corporation
Inventor： Xun Zhang , Chaitanya Palusa , Dawei Huang , Muthukumar Vairavan , Jianghui Su
CPC classification number: H04L25/03057 , H04B1/16
Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, the equalized input signal to generate multiple samples of a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.
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公开(公告)号：US20220191071A1
公开(公告)日：2022-06-16
申请号：US17648899
申请日：2022-01-25
Applicant: Oracle International Corporation
Inventor： Xun Zhang , Chaitanya Palusa , Dawei Huang , Muthukumar Vairavan , Jianghui Su
Abstract: A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, the equalized input signal to generate multiple samples of a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.
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公开(公告)号：US10257121B1
公开(公告)日：2019-04-09
申请号：US15722349
申请日：2017-10-02
Applicant: Oracle International Corporation
Inventor： Zuxu Qin , Baoqing Huang , Dawei Huang , Kuai Yin , Maoqing Yao , Philip Kwan
IPC: H04L9/06 , B23P19/04 , H04L12/935
Abstract: Embodiments include systems and methods for transmitting data over high-speed data channels in context of serializer/deserializer circuits. Some embodiments include a novel full-rate source-series-terminated (SST) transmitter driver architecture with output charge sharing isolation. Certain implementations have a programmable floating tap (e.g., in addition to standard taps) with both positive and negative FIR values and cursor reduction, which can help achieve large FIR range and high channel equalization capability. Some embodiments operate with multi-phase clocking having phased clock error correction, which can facilitate operation with low-jitter and low-DCD clocks. Some implementations also include novel output inductor structures that are disposed to partially overlap output interface bumps.
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