公开(公告)号：US5745723A

公开(公告)日：1998-04-28

申请号：US721305

申请日：1996-09-26

申请人： Masahito Matsuo ,  Toru Shimizu ,  Toyohiko Yoshida

发明人： Masahito Matsuo ,  Toru Shimizu ,  Toyohiko Yoshida

IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/38 ,  G06F11/36

CPC分类号： G06F9/3865 ,  G06F11/3648 ,  G06F9/3001 ,  G06F9/30149 ,  G06F9/3822 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3869 ,  G06F9/3875

摘要： A a data processing system capable of returning correctly from an exceptional processing by the same processing as that in the case of executing instructions one by one without particular control even if an exception occurs in the midway of the instruction processing, and capable of selecting a mode for executing instructions one by one in debugging or a test, so that a plurality of instructions are executed in parallel with simple control.

公开(公告)号：US5461715A

公开(公告)日：1995-10-24

申请号：US64727

申请日：1993-05-19

申请人： Masahito Matsuo ,  Toru Shimizu ,  Toyohiko Yoshida

发明人： Masahito Matsuo ,  Toru Shimizu ,  Toyohiko Yoshida

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F9/302 ,  G06F11/36

CPC分类号： G06F9/3001 ,  G06F11/3648 ,  G06F9/30149 ,  G06F9/3816 ,  G06F9/3822 ,  G06F9/3865 ,  G06F9/3869 ,  G06F9/3875

摘要： A a data processing system capable of returning correctly from an exceptional processing by the same processing as that in the case of executing instructions one by one without particular control even if an exception occurs in the midway of the instruction processing, and capable of selecting a mode for executing instructions one by one in debugging or a test so that a plurality of instructions are executed in parallel with simple control.

摘要翻译： 一种数据处理系统，能够通过与执行指令的情况相同的处理从异常处理中正确地返回，即使在指令处理的中途发生异常，也无需特别的控制，能够选择模式 用于在调试或测试中逐个执行指令，使得与简单控制并行地执行多个指令。

公开(公告)号：US5193205A

公开(公告)日：1993-03-09

申请号：US317253

申请日：1989-02-28

申请人： Masahito Matsuo ,  Toyohiko Yoshida

发明人： Masahito Matsuo ,  Toyohiko Yoshida

IPC分类号： G06F9/32 ,  G06F9/38 ,  G06F9/40

CPC分类号： G06F9/3806 ,  G06F9/30054 ,  G06F9/321 ,  G06F9/3842 ,  G06F9/3867

摘要： A data processor in accordance with the present invention makes it possible to perform pre-branch processing with respect to a return address in the initial stage of pipeline processing also on a subroutine return instruction, and therefore by providing a stack memory (PC stack) dedicated to a program counter (PC) for storing only return addresses of the subroutine return instruction, in executing a subroutine call instruction in an execution stage of a pipeline processing mechanism, the return address from the subroutine is pushed to the PC stack, and the pre-branch processing is performed to the address popped from the PC stack in decoding the subroutine return instruction in an instruction decoding stage.

摘要翻译： 根据本发明的数据处理器使得可以在流水线处理的初始阶段对子程序返回指令执行关于返回地址的预分支处理，因此通过提供专用的堆栈存储器（PC堆栈） 到用于仅存储子程序返回指令的返回地址的程序计数器（PC），在执行流水线处理机构的执行阶段中的子程序调用指令时，将子程序的返回地址推送到PC堆栈， 在指令解码阶段对子例程返回指令进行解码时，对从PC堆栈弹出的地址进行分支处理。

公开(公告)号：US4974158A

公开(公告)日：1990-11-27

申请号：US506498

申请日：1990-04-09

申请人： Yukari Watanabe ,  Toyohiko Yoshida ,  Masahito Matsuo ,  Yuichi Saito ,  Toru Shimizu

发明人： Yukari Watanabe ,  Toyohiko Yoshida ,  Masahito Matsuo ,  Yuichi Saito ,  Toru Shimizu

IPC分类号： G06F9/38

CPC分类号： G06F9/3824 ,  G06F9/3863 ,  G06F9/3867

摘要： This invention relates to a data processor with pipelining system, which is provided with at least two stages having working stackpointer respectively, and so constructed that each stage can independently refer to the working stackpointer corresponding to each stage, and each working stackpointer corresponding to each stage is renewed synchronizing with pipelining processing, so that when execution of a plural instructions including designation of operands under stack-push addressing mode and stack-pop addressing mode, result of address calculation executed at the address calculation stage is sequentially transferred to corresponding working stackpointers synchronizing with the transfer of instructions through the stages of pipeline, thereby being possible for the data processor to smoothly execute pipelining process.

摘要翻译： 本发明涉及一种具有流水线系统的数据处理器，其具有分别具有工作堆栈指针的至少两个级，并且构造成使得每个级可以独立地指代对应于每个级的工作堆栈指针，并且每个工作堆栈指针对应于每个级 与流水线处理同步地更新，使得当在堆栈推送寻址模式和堆栈弹出寻址模式下执行包括指定操作数的多个指令时，在地址计算阶段执行的地址计算的结果被顺序地传送到相应的工作堆栈指针同步 通过管道传送指令，从而可以使数据处理器顺利地执行流水线处理。

公开(公告)号：US4796175A

公开(公告)日：1989-01-03

申请号：US34093

申请日：1987-04-02

申请人： Masahito Matsuo ,  Toyohiko Yoshida

发明人： Masahito Matsuo ,  Toyohiko Yoshida

IPC分类号： G06F9/38 ,  G06F12/08

CPC分类号： G06F9/3814 ,  G06F9/3802 ,  G06F9/381

摘要： A microprocessor has a main memory, an instruction execution unit, and instruction queue for prefetching a series of instructions from the main memory, and an instruction cache. The instruction cache prefetches and stores an instruction next to those stored in the instruction queue by use of its address tag as an index when an amount of data fetched in the instruction queue is below a constant value. The fetching of the next instruction into the instruction queue from the instruction cache is achieved at the time to execute the same instruction again.

摘要翻译： 微处理器具有主存储器，指令执行单元和用于从主存储器预取一系列指令的指令队列和指令高速缓存。 当指令队列中读取的数据量低于常数值时，指令高速缓存将存储在指令队列中的指令与存储在指令队列中的指令相对应地存储并存储指令。 在执行相同的指令时，实现从指令高速缓存取出下一条指令到指令队列中。

公开(公告)号：US07346760B2

公开(公告)日：2008-03-18

申请号：US09855594

申请日：2001-05-16

申请人： Toyohiko Yoshida ,  Akira Yamada ,  Hisakazu Sato

发明人： Toyohiko Yoshida ,  Akira Yamada ,  Hisakazu Sato

IPC分类号： G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3814 ,  G06F7/5443 ,  G06F9/3802 ,  G06F9/381 ,  G06F9/3822 ,  G06F9/3875

摘要： When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory bank can be precharged to allow reduction of power consumption. Since the first and second pipeline cycles are effected in parallel, the throughput of the instruction memory can be improved.

摘要翻译： 当从多个存储体获取指令时，生成对应于存储器组的选择的第一流水线循环和对应于指令读出的第二流水线循环，以执行流水线处理。 只有选定的存储体可以被预先充电，以减少功耗。 由于第一和第二流水线周期是并行实现的，因此可以提高指令存储器的吞吐量。

公开(公告)号：US06333571B1

公开(公告)日：2001-12-25

申请号：US09577969

申请日：2000-05-25

申请人： Eiichi Teraoka ,  Toyohiko Yoshida

发明人： Eiichi Teraoka ,  Toyohiko Yoshida

IPC分类号： H01H4700

CPC分类号： H03K19/0013 ,  H01L27/092 ,  Y10T307/76 ,  Y10T307/826

摘要： In accordance with selection signals corresponding to an operation mode from a mode detection circuit, the voltage levels of back gate voltages applied to the back gates of MOS transistors included in internal circuitry are selected, by the selection signals, among the voltages from voltage generation circuits for generating a plurality of voltages having different voltage levels. The threshold voltage and the drive current of the MOS transistor are adjusted in accordance with the operation mode, and the semiconductor integrated circuit device which operates at high speed with low current consumption can be achieved.

摘要翻译： 根据与来自模式检测电路的操作模式对应的选择信号，通过选择信号选择施加到内部电路中的MOS晶体管的背栅极的背栅电压的电压电平，来自电压产生电路 用于产生具有不同电压电平的多个电压。 根据操作模式调整MOS晶体管的阈值电压和驱动电流，并且可以实现以低电流消耗高速运行的半导体集成电路器件。

公开(公告)号：US6115806A

公开(公告)日：2000-09-05

申请号：US56650

申请日：1998-04-08

申请人： Toyohiko Yoshida

发明人： Toyohiko Yoshida

IPC分类号： G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F3/30

CPC分类号： G06F9/30167 ,  G06F9/30145 ,  G06F9/3842 ,  G06F9/3853 ,  G06F9/3885

摘要： In a data processor, using a format field which specifies the number of operation fields of an instruction code and an order of execution of operations, the number of operations and the order of operation executions are flexibly controlled and the necessity of a null operation is reduced, and decoders operate in parallel each decoding only one operation having a specific function which has a dependency on an operation execution mechanism, so that the operation fields of the instruction code are decoded in parallel by a number of decoders. While the data processor is basically a VLIW type data processor, more types of operations can be specified by the operation fields, and coding efficiency of instructions is improved since the number of operation fields and the order of operation executions are flexibly controlled and the necessity of a null operation is reduced by means of the format field which specifies the number of the operation and the order of the operation executions.

摘要翻译： 在数据处理器中，使用指定指令代码的操作字段的数量的格式字段和操作的执行顺序，灵活地控制操作次数和操作执行顺序，并且减少空操作的必要性 并且解码器并行操作，每个仅解码具有与操作执行机构相关的特定功能的一个操作，使得指令代码的操作字段由多个解码器并行解码。 虽然数据处理器基本上是一个VLIW型数据处理器，但操作领域可以指定更多类型的操作，并且由于操作字段的数量和操作执行的顺序被灵活地控制，并且必须 通过指定操作次数和操作执行顺序的格式字段来减少空操作。

公开(公告)号：US5522053A

公开(公告)日：1996-05-28

申请号：US291963

申请日：1994-08-17

申请人： Toyohiko Yoshida ,  Masahito Matuo

发明人： Toyohiko Yoshida ,  Masahito Matuo

IPC分类号： G06F9/32 ,  G06F9/38

CPC分类号： G06F9/32 ,  G06F9/38

摘要： An instruction decoding device for a data processor which is capable of predicting a branch address is disclosed. A program counter value calculation device can be used to calculate the branch target address. An address calculation device can be used to calculate an operand address. The address calculation device can calculate the operand address by adding the instruction length of the branch instruction and the program counter value of the branch instruction. In this way the apparatus performs branching processing for the unconditional branch instructions, conditional branch instructions, subroutine branch instructions and loop control instructions at the instruction decoding stage to suppress disturbances in the pipeline processing.

摘要翻译： 公开了一种能够预测分支地址的数据处理器的指令解码装置。 可以使用程序计数器值计算装置来计算分支目标地址。 地址计算装置可用于计算操作数地址。 地址计算装置可以通过添加分支指令的指令长度和分支指令的程序计数器值来计算操作数地址。 以这种方式，设备在指令解码阶段对无条件转移指令，条件转移指令，子程序转移指令和循环控制指令执行分支处理，以抑制流水线处理中的干扰。

公开(公告)号：US5465376A

公开(公告)日：1995-11-07

申请号：US59943

申请日：1993-05-05

申请人： Toyohiko Yoshida

发明人： Toyohiko Yoshida

IPC分类号： G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F9/46

CPC分类号： G06F9/3802 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/34 ,  G06F9/382 ,  G06F9/3863 ,  G06F9/3877

摘要： In a data processing system, the program counter (PC) values of coprocessor (CP) instructions are stored in a queue of a CP, and the stored PC value is not erased until the CP has completed executing the instruction. The need for a queue is caused by the pipeline in the CP. Three instructions may be executing concurrently and an exception may occur for any one of them. Accordingly, for example, at least 3 PC values must be stored in the queue. Early overwriting is prevented by making the queue 4 words deep. Also, the CP must assert a CPST signal before accepting a new command from the micro processor (MC). Thus, if the pipeline is full the CPST signal will not be asserted and the MP must wait before storing the new PC value in the queue. Instead of the entire PC, only an entry point is transferred to the CP. When only four PC values are saved, the entry point is only two bits and may be transferred along with the command information in a single bus cycle. If there are more than one CP, a program status word (PSW) includes a CPID for identifying which CP is to execute a received CP instruction. The queue and PCID system is only used for the first CP. In the event that an exception occurs, the entry point is transferred back to the MP and the PC of the instruction that took the exception is provided.

摘要翻译： 在数据处理系统中，协处理器（CP）指令的程序计数器（PC）值被存储在CP的队列中，并且存储的PC值不被擦除，直到CP完成执行指令。 队列的需要是由CP中的管道引起的。 三个指令可能同时执行，并且任何一个可能发生异常。 因此，例如，必须在队列中存储至少3个PC值。 通过使队列4字深入，可以防止早期重写。 此外，CP必须在接收来自微处理器（MC）的新命令之前先断言CPST信号。 因此，如果流水线已满，则将不会断言CPST信号，并且在将新的PC值存储在队列中之前，MP必须等待。 而不是整个PC，只有一个入口点被传送到CP。 当仅保存四个PC值时，入口点只有两个位，并且可以在单个总线周期内与命令信息一起传输。 如果存在多于一个CP，则程序状态字（PSW）包括用于识别哪个CP执行接收到的CP指令的CPID。 队列和PCID系统仅用于第一个CP。 在发生异常的情况下，将入口点传回MP，提供异常指令的PC。