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发明授权
US07346760B2 Data processing apparatus of high speed process using memory of low speed and low power consumption 有权
数据处理装置采用低速，低功耗的存储器

Data processing apparatus of high speed process using memory of low speed and low power consumption
摘要：
When fetching an instruction from a plurality of memory banks, a first pipeline cycle corresponding to selection of a memory bank and a second pipeline cycle corresponding to instruction readout are generated to carry out a pipeline process. Only the selected memory bank can be precharged to allow reduction of power consumption. Since the first and second pipeline cycles are effected in parallel, the throughput of the instruction memory can be improved.
摘要（中）：

当从多个存储体获取指令时，生成对应于存储器组的选择的第一流水线循环和对应于指令读出的第二流水线循环，以执行流水线处理。 只有选定的存储体可以被预先充电，以减少功耗。 由于第一和第二流水线周期是并行实现的，因此可以提高指令存储器的吞吐量。

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