公开(公告)号：US20140315380A1

公开(公告)日：2014-10-23

申请号：US13866293

申请日：2013-04-19

Applicant: International Business Machines Corporation

Inventor： Sivananda K. Kanakasabapathy ,  Chiahsun Tseng ,  Yongan Xu ,  Yunpeng Yin

IPC: H01L21/768 ,  H01L21/308

CPC classification number: H01L21/3083 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/31144 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76816 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method including forming a tetra-layer hardmask above a substrate, the tetra-layer hardmask including a second hardmask layer above a first hardmask layer; removing a portion of the second hardmask layer of the tetra-layer hardmask within a pattern region of a structure comprising the substrate and the tetra-layer hardmask; forming a set of sidewall spacers above the tetra-layer hardmask to define a device pattern; and transferring a portion of the device pattern into the substrate and within the pattern region of the structure.

Abstract translation: 一种包括在衬底上形成四层硬掩模的方法，所述四层硬掩模包括在第一硬掩模层上方的第二硬掩模层; 在包括所述基底和所述四层硬掩模的结构的图案区域内去除所述四层硬掩模的所述第二硬掩模层的一部分; 在所述四层硬掩模之上形成一组侧壁间隔物以限定器件图案; 以及将所述器件图案的一部分转移到所述衬底中并且在所述结构的图案区域内。

公开(公告)号：US11784120B2

公开(公告)日：2023-10-10

申请号：US17480824

申请日：2021-09-21

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  James J. Kelly ,  Muthumanickam Sankarapandian ,  Yongan Xu ,  Hsueh-Chung Chen ,  Daniel J. Vincent

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L21/027

CPC classification number: H01L23/5226 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5283 ,  H01L21/0276

Abstract: A semiconductor device includes a stack structure having at least first, second and third interconnect levels. Each interconnect level has a patterned metal conductor including a first metallic material. A via spans the second and third interconnect levels and electrically couples with the patterned metal conductor of the first interconnect level. At least a segment of the super via includes a second metallic material different from the first metallic material.

公开(公告)号：US10975464B2

公开(公告)日：2021-04-13

申请号：US15948007

申请日：2018-04-09

Applicant: International Business Machines Corporation

Inventor： Ekmini Anuja De Silva ,  Yongan Xu ,  Abraham Arceo de la Pena ,  Chih-Chao Yang

IPC: H01L21/00 ,  C23C14/34 ,  H01L21/285 ,  C23C14/54 ,  C23C14/35

Abstract: A method of forming a semiconductor structure includes, in a radio frequency (RF) deposition chamber, depositing a titanium film using physical vapor deposition and forming a graded hard mask film by reactive sputtering the titanium film with nitrogen in the RF deposition chamber. The graded hard mask film is a titanium nitride film with a graded vertical concentration of nitrogen. The method may further include, during deposition of the titanium film and during formation of the graded hard mask film, modulating one or more parameters of the RF deposition chamber, such as modulating an auto capacitance tuner (ACT) current, modulating the RF power, and modulating the pressure of the RF deposition chamber.

公开(公告)号：US10937653B2

公开(公告)日：2021-03-02

申请号：US16669835

申请日：2019-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hsueh-Chung Chen ,  Yongan Xu ,  Lawrence A. Clevenger ,  Yann Mignot ,  Cornelius Brown Peethala

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/02 ,  H01L21/3105 ,  G03F7/00 ,  G03F7/16 ,  G03F7/20 ,  G03F7/09

Abstract: A method for fabricating a semiconductor device integrating a multiple patterning scheme includes forming a memorization layer over a plurality of mandrels and a plurality of non-mandrels, and applying an exposure scheme to the memorization layer to form at least one mandrel cut pattern and at least one non-mandrel cut pattern.

公开(公告)号：US10825720B2

公开(公告)日：2020-11-03

申请号：US16112286

申请日：2018-08-24

Applicant: International Business Machines Corporation

Inventor： Yann Mignot ,  Yongan Xu ,  Muthumanickam Sankarapandian

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532 ,  H01L21/033 ,  H01L21/02 ,  H01L21/311

Abstract: Techniques for single trench damascene interconnect formation using TiN HMO are provided. In one aspect, a method for forming interconnects on a substrate includes: forming an underlayer on the substrate; forming a hardmask on the underlayer; patterning trenches in the hardmask that extend down to the underlayer; forming the interconnects in the trenches; removing the hardmask; and burying the interconnects in an ILD. The trenches can be patterned in the hardmask using a process such as sidewall image transfer. An interconnect structure is also provided.

公开(公告)号：US20200066526A1

公开(公告)日：2020-02-27

申请号：US16669861

申请日：2019-10-31

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hsueh-Chung Chen ,  Yongan Xu ,  Lawrence A. Clevenger ,  Yann Mignot ,  Cornelius Brown Peethala

IPC: H01L21/033 ,  G03F7/00 ,  H01L21/027 ,  G03F7/20 ,  G03F7/09 ,  H01L21/02 ,  H01L21/3105 ,  G03F7/16

Abstract: A semiconductor device includes at least one mandrel including a dielectric material, and at least one non-mandrel including a hard mask material having an etch property substantially similar to that of the dielectric material.

公开(公告)号：US10559467B2

公开(公告)日：2020-02-11

申请号：US16001426

申请日：2018-06-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John Christopher Arnold ,  Sean D. Burns ,  Yann Alain Marcel Mignot ,  Yongan Xu

IPC: H01L21/02 ,  H01L21/027 ,  H01L21/033 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31 ,  H01L21/311 ,  H01L21/768

Abstract: Selective gas etching for self-aligned pattern transfer uses a first block and a separate second block formed in a sacrificial layer to transfer critical dimensions to a desired final layer using a selective gas etching process. The first block is a first hardmask material that can be plasma etched using a first gas, and the second block is a second hardmask material that can be plasma etched using a second gas separate from the first gas. The first hardmask material is not plasma etched using the second gas, and the second hardmask material is not plasma etched using the first gas.

公开(公告)号：US10551742B2

公开(公告)日：2020-02-04

申请号：US15848471

申请日：2017-12-20

Applicant: International Business Machines Corporation

Inventor： Yongan Xu ,  Jing Guo ,  Ekmini A. De Silva ,  Oleg Gluschenkov

IPC: G03F7/20 ,  H01L21/027 ,  G03F7/075 ,  G03F7/085

Abstract: An EUV lithographic structure and methods according to embodiments of the invention includes an EUV photosensitive resist layer disposed directly on an oxide hardmask layer, wherein the oxide hardmask layer is doped with dopant ions to form a doped oxide hardmask layer so as to improve adhesion between the EUV lithographic structure and the oxide hardmask. The EUV lithographic structure is free of a separate adhesion layer.

公开(公告)号：US20190273127A1

公开(公告)日：2019-09-05

申请号：US15911626

申请日：2018-03-05

Applicant: International Business Machines Corporation

Inventor： Peng Xu ,  Kangguo Cheng ,  Xuefeng Liu ,  Chi-Chun Liu ,  Yongan Xu

IPC: H01L49/02 ,  H01L21/3105

Abstract: Techniques for generating enhanced inductors and other electronic devices are presented. A device generator component (DGC) performs directed-self assembly (DSA) co-polymer deposition on a circular guide pattern formed in low-k dielectric film, and DSA annealing to form two polymers in the form of alternating concentric rings; performs a loop cut in the concentric rings to form concentric segments; fills the cut portion with insulator material; selectively removes first polymer, fills the space with low-k dielectric, and planarizes the surface; selectively removes the second polymer, fills the space with conductive material, and planarizes the surface; deposits low-k film on top of the concentric segments and insulator material that filled the loop cut portion; forms vias in the low-k film, wherein each via spans from an end of one segment to an end of another segment; and fills vias with conductive material to form conductive connectors to form substantially spiral conductive structure.

公开(公告)号：US10396179B2

公开(公告)日：2019-08-27

申请号：US15948563

申请日：2018-04-09

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Xuefeng Liu ,  Peng Xu ,  Yongan Xu

IPC: H01L29/786 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/49 ,  H01L21/311

Abstract: A method of forming a vertical transport field effect transistors with uniform bottom spacer thickness, including, forming a plurality of vertical fins on a substrate, forming a protective liner layer on the plurality of vertical fins, forming a sacrificial liner on the protective liner layer, forming a spacer liner on a portion of the sacrificial liner, wherein at least a top surface of the sacrificial liner on each of the vertical fins is exposed, converting the exposed portion of the sacrificial liner on each of the vertical fins to a conversion cap, and removing the conversion cap from each of the vertical fins to expose an upper portion of each vertical fin.