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    TEG PATTERN FOR DETECTING VOID IN DEVICE ISOLATION LAYER AND METHOD OF FORMING THE SAME
    22.
    发明申请
    TEG PATTERN FOR DETECTING VOID IN DEVICE ISOLATION LAYER AND METHOD OF FORMING THE SAME 失效
    用于检测设备隔离层中的空穴的TEG图案及其形成方法

    公开(公告)号：US20090283764A1

    公开(公告)日：2009-11-19

    申请号：US12435161

    申请日：2009-05-04

    Applicant: Tae-Gyun Kim ,  Dong-Suk Shin ,  Joo-Won Lee ,  Ha-Jin Lim

    Inventor： Tae-Gyun Kim ,  Dong-Suk Shin ,  Joo-Won Lee ,  Ha-Jin Lim

    IPC: H01L23/544

    CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Provided is a test element group (TEG) pattern for detecting a void in a device isolation layer. The TEG pattern includes active regions which are parallel to each other and extend in a first direction, a device isolation layer that separates the active regions, a first contact that is formed across the device isolation layer and a first one of the active regions that contacts a surface of the device isolation layer, and a second contact that is formed across the device isolation layer and a second one of the active regions that contacts another surface of the device isolation layer.

    Abstract translation: 提供了用于检测器件隔离层中的空隙的测试元件组（TEG）图案。 TEG图案包括彼此平行并在第一方向上延伸的有源区域，分离有源区域的器件隔离层，跨过器件隔离层形成的第一接触和接触的第一有源区域 器件隔离层的表面，以及跨过器件隔离层形成的第二接触和接触器件隔离层的另一表面的第二有源区。

    Semiconductor devices having nitrogen-incorporated active region and methods of fabricating the same
    23.
    发明申请
    Semiconductor devices having nitrogen-incorporated active region and methods of fabricating the same 有权
    具有氮结合有源区的半导体器件及其制造方法

    公开(公告)号：US20070001241A1

    公开(公告)日：2007-01-04

    申请号：US11396702

    申请日：2006-04-04

    Applicant: Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung ,  Yun Kim ,  Min Kim

    Inventor： Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung ,  Yun Kim ,  Min Kim

    IPC: H01L29/94

    CPC classification number: H01L21/823807 ,  H01L21/823857

    Abstract: A semiconductor device may include a semiconductor substrate having a first region and a second region. The nitrogen-incorporated active region may be formed within the first region. A first gate electrode may be formed on the nitrogen-incorporated active region. A first gate dielectric layer may be interposed between the nitrogen-incorporated active region and the first gate electrode. The first gate dielectric layer may include a first dielectric layer and a second dielectric layer. The second dielectric layer may be a nitrogen contained dielectric layer. A second gate electrode may be formed on the second region. A second gate dielectric layer may be interposed between the second region and the second gate electrode. The first gate dielectric layer may have the same or substantially the same thickness as the second gate dielectric layer, and the nitrogen contained dielectric layer may contact with the nitrogen-incorporated active region.

    Abstract translation: 半导体器件可以包括具有第一区域和第二区域的半导体衬底。 可以在第一区域内形成含氮的有源区。 可以在引入氮的有源区上形成第一栅电极。 第一栅极电介质层可插入在引入氮的有源区和第一栅电极之间。 第一栅介质层可以包括第一介电层和第二介电层。 第二电介质层可以是含氮介电层。 第二栅极电极可以形成在第二区域上。 可以在第二区域和第二栅电极之间插入第二栅极电介质层。 第一栅极介电层可以具有与第二栅极介电层相同或基本相同的厚度，并且含氮介电层可以与引入氮的有源区接触。

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    24.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20150206974A1

    公开(公告)日：2015-07-23

    申请号：US14602660

    申请日：2015-01-22

    Applicant: Ha-Jin Lim ,  Hyeong-Joon Kim ,  Nae-In Lee

    Inventor： Ha-Jin Lim ,  Hyeong-Joon Kim ,  Nae-In Lee

    IPC: H01L29/78 ,  H01L29/36 ,  H01L29/20

    CPC classification number: H01L29/66818 ,  H01L21/02241 ,  H01L21/28264 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

    Abstract: A semiconductor device includes a semiconductor substrate comprising a group III element and a group V element, and a gate structure on the semiconductor substrate. The semiconductor substrate includes a first region which contacts a bottom surface of the gate structure and a second region which is disposed under the first region. The concentration of the group III element in the first region is lower than that of the group V element in the first region, and the concentration of the group III element in the second region is substantially equal to that of the group V element in the second region.

    Abstract translation: 半导体器件包括包含III族元素和V族元素的半导体衬底，以及在半导体衬底上的栅极结构。 半导体衬底包括接触栅极结构的底表面的第一区域和设置在第一区域下方的第二区域。 第一区域中的III族元素的浓度低于第一区域中的V族元素的浓度，并且第二区域中的III族元素的浓度基本上等于第二区域中的第V族元素的浓度 地区。

    Method of fabricating semiconductor integrated circuit device
    25.
    发明授权
    Method of fabricating semiconductor integrated circuit device 有权
    制造半导体集成电路器件的方法

    公开(公告)号：US08227308B2

    公开(公告)日：2012-07-24

    申请号：US12647806

    申请日：2009-12-28

    Applicant: Ha-Jin Lim ,  Dong-Suk Shin ,  Pan-Kwi Park ,  Jun-Jung Kim ,  Tae-Gyun Kim

    Inventor： Ha-Jin Lim ,  Dong-Suk Shin ,  Pan-Kwi Park ,  Jun-Jung Kim ,  Tae-Gyun Kim

    IPC: H01L21/8238

    CPC classification number: H01L21/28518 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7843

    Abstract: A method of fabricating a semiconductor integrated circuit (IC) device can include forming a first silicide layer on at least a portion of a transistor on a substrate, forming nitrogen in the first silicide layer to form a second silicide layer, forming a first stress layer having a tensile stress on the substrate having the transistor formed thereon, and irradiating the first stress layer with ultraviolet (UV) light to form a second stress layer having greater tensile stress than the first stress layer.

    Abstract translation: 制造半导体集成电路（IC）器件的方法可以包括在衬底上的晶体管的至少一部分上形成第一硅化物层，在第一硅化物层中形成氮以形成第二硅化物层，形成第一应力层 在其上形成有晶体管的衬底上具有拉伸应力，并且用紫外线（UV）光照射第一应力层以形成具有比第一应力层更大的拉伸应力的第二应力层。

    Transistors with Multilayered Dielectric Films and Methods of Manufacturing Such Transistors
    26.
    发明申请
    Transistors with Multilayered Dielectric Films and Methods of Manufacturing Such Transistors 有权
    具有多层介质膜的晶体管及其制造方法

    公开(公告)号：US20110287622A1

    公开(公告)日：2011-11-24

    申请号：US13195935

    申请日：2011-08-02

    Applicant: Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung

    Inventor： Ha-Jin Lim ,  Jong-Ho Lee ,  Hyung-Suk Jung

    IPC: H01L21/28

    CPC classification number: H01L21/28185 ,  H01L21/28079 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/513 ,  H01L29/517

    Abstract: Transistors that include multilayered dielectric films on a channel region are provided. The multilayered dielectric comprises a lower dielectric film that may have a thickness that is at least 50% the thickness of the multilayered dielectric film and that comprises a metal oxide, a metal silicate, an aluminate, or a mixture thereof, and an upper dielectric film on the lower dielectric film, the upper dielectric film comprising a Group III metal oxide, Group III metal nitride, Group XIII metal oxide or Group XIII metal nitride. A gate electrode is provided on the multilayered dielectric film.

    Abstract translation: 提供了在通道区​​域上包括多层电介质膜的晶体管。 多层电介质包括下电介质膜，该电介质膜的厚度至少为多层电介质膜的厚度的50％，并且包括金属氧化物，金属硅酸盐，铝酸盐或其混合物，以及上电介质膜 在下介电膜上，上电介质膜包含III族金属氧化物，III族金属氮化物，第ⅩⅢ族金属氧化物或第ⅩⅢ族金属氮化物。 在多层电介质膜上设置栅电极。

    Method of fabricating metal silicate layer using atomic layer deposition technique
    27.
    发明授权
    Method of fabricating metal silicate layer using atomic layer deposition technique 有权
    使用原子层沉积技术制造金属硅酸盐层的方法

    公开(公告)号：US07651729B2

    公开(公告)日：2010-01-26

    申请号：US11127748

    申请日：2005-05-12

    Applicant: Yun-Seok Kim ,  Jong-Pyo Kim ,  Ha-Jin Lim ,  Jae-Eun Park ,  Hyung-Suk Jung ,  Jong-Ho Lee ,  Jong-Ho Yang

    Inventor： Yun-Seok Kim ,  Jong-Pyo Kim ,  Ha-Jin Lim ,  Jae-Eun Park ,  Hyung-Suk Jung ,  Jong-Ho Lee ,  Jong-Ho Yang

    IPC: C23C16/00

    CPC classification number: C23C16/401 ,  C23C16/45529 ,  C23C16/45531

    Abstract: There are provided methods of fabricating a metal silicate layer on a semiconductor substrate using an atomic layer deposition technique. The methods include performing a metal silicate layer formation cycle at least one time in order to form a metal silicate layer having a desired thickness. The metal silicate layer formation cycle includes an operation of repeatedly performing a metal oxide layer formation cycle K times and an operation of repeatedly performing a silicon oxide layer formation cycle Q times. K and Q are integers ranging from 1 to 10 respectively. The metal oxide layer formation cycle includes the steps of supplying a metal source gas to a reactor containing the substrate, exhausting the metal source gas remaining in a reactor to clean the inside of the reactor, and then supplying an oxide gas into the reactor. The silicon oxide layer formation cycle includes supplying a silicon source gas, exhausting the silicon source gas remaining in the reactor to clean the inside of the reactor, and then supplying an oxide gas into the reactor.

    Abstract translation: 提供了使用原子层沉积技术在半导体衬底上制造金属硅酸盐层的方法。 所述方法包括至少一次执行金属硅酸盐层形成循环以形成具有所需厚度的金属硅酸盐层。 金属硅酸盐层形成循环包括重复进行金属氧化物层形成循环K次的操作和重复进行氧化硅层形成循环Q次的操作。 K和Q分别为1〜10的整数。 金属氧化物层形成循环包括将金属源气体供给到含有基板的反应器，排出留在反应器内的金属源气体，清洗反应器内部，然后向反应器供给氧化气体的工序。 氧化硅层形成循环包括提供硅源气体，排出留在反应器中的硅源气体以清洁反应器的内部，然后将氧化物气体供应到反应器中。

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