公开(公告)号：US10417363B1

公开(公告)日：2019-09-17

申请号：US15391594

申请日：2016-12-27

Applicant: Cadence Design Systems, Inc.

Inventor： Jagjot Kaur ,  Priyanka Dasgupta ,  Pratyush Aditya Kothamasu ,  Vivek Chickermane

IPC: G06F17/50 ,  G06F11/27

Abstract: Embodiments relate to methodologies for applying multibit cell merging to functional shift registers, thereby saving area, reducing scan-wirelength, saving power and reducing wiring congestion in integrated circuit designs. In embodiments, during synthesis, shift registers in a design are identified. In these and other embodiments, in identified shift registers, functional shift register flip-flops are merged into non-scan multi-bit flip-flops using a physically aware approach.

公开(公告)号：US08904256B1

公开(公告)日：2014-12-02

申请号：US13673522

申请日：2012-11-09

Applicant: Cadence Design Systems, Inc.

Inventor： Krishna Chakravadhanula ,  Vivek Chickermane ,  Dale Meehl

IPC: G01R31/28 ,  G01R31/3177

CPC classification number: G01R31/318547

Abstract: A method and apparatus to apply compressed test patterns using a very pin-limited test apparatus to a chip design for use in semiconductor manufacturing test is disclosed. Compression circuitry is inserted into the circuit design and the compressed signals manipulated for communication over a serial interface. On a test apparatus, ATPG may be run, assuming a parallel test interface, resulting in test patterns that may be compressed into a parallel format and then converted into a serial signal. On chip, the serial signal is parallelized, decompressed, and then shifted into the scan chains. An inserted controller generates clocks and various control signals. Conventional test patterns from ATPG may be generated and applied during testing without the need to modify the ATPG program saving time and resources. Hierarchical testing of integrated circuits built with a multiplicity of cores, each having its own embedded compression logic, is also supported.

Abstract translation: 公开了一种使用非常针脚限制的测试装置将压缩测试图案应用于用于半导体制造测试中的芯片设计的方法和装置。 压缩电路插入到电路设计中，压缩信号被操纵以通过串行接口进行通信。 在测试装置上，可以运行ATPG，假设为并行测试接口，导致测试模式可能被压缩为并行格式，然后转换为串行信号。 在芯片上，串行信号并行化，解压缩，然后移入扫描链。 插入的控制器产生时钟和各种控制信号。 可以在测试过程中生成和应用ATPG的常规测试模式，而无需修改ATPG程序节省时间和资源。 还支持使用多个内核构建的集成电路的分层测试，每个核心都具有自己的嵌入式压缩逻辑。

公开(公告)号：US08650524B1

公开(公告)日：2014-02-11

申请号：US13673579

申请日：2012-11-09

Applicant: Cadence Design Systems, Inc.

Inventor： Krishna Chakravadhanula ,  Vivek Chickermane ,  Dale Meehl

IPC: G06F17/50

CPC classification number: G06F17/505 ,  G06F2217/14

Abstract: A method and apparatus to apply compressed test patterns using a very pin-limited test apparatus to a chip design for use in semiconductor manufacturing test is disclosed. Compression circuitry is inserted into the circuit design and the compressed signals manipulated for communication over a serial interface. On a test apparatus, ATPG may be run, assuming a parallel test interface, resulting in test patterns that may be compressed into a parallel format and then converted into a serial signal. On chip, the serial signal is parallelized, decompressed, and then shifted into the scan chains. An inserted controller generates clocks and various control signals. Conventional test patterns from ATPG may be generated and applied during testing without the need to modify the ATPG program saving time and resources. Hierarchical testing of integrated circuits built with a multiplicity of cores, each having its own embedded compression logic, is also supported.

公开(公告)号：US10955470B1

公开(公告)日：2021-03-23

申请号：US16218954

申请日：2018-12-13

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Brian Edward Foutz ,  Christos Papameletis ,  Vivek Chickermane ,  Krishna Vijaya Chakravadhanula

IPC: G01R31/3177 ,  G01R31/317 ,  G06F30/33 ,  G06F30/392 ,  G06F30/398

Abstract: Methods and design system for generating 2-dimensional distribution architecture for testing integrated circuit design that utilizes double grid to minimize interdependencies between grid cells and the associated functional logic to facilitate the a physically efficient scan of integrated circuit designs, that simultaneously minimizes required test application time (“TAT”), test data volume, tester memory and cost associated with design for test (“DFT”), while also retaining test coverage. An additional grid parallel to a 2-dimensional XOR grid may be implemented that improves the quality of test coverage by optimally adding additional data inputs which decreases correlations between grid cells. A column spreader may feed data into column wires and row spreader may feed data into column wires. The double grid allows data to be fed into two wires, row and column, respectively, which provides twice as much stimulus data in each direction, without significantly increasing the wiring used to build the grid.

公开(公告)号：US10796041B1

公开(公告)日：2020-10-06

申请号：US16389733

申请日：2019-04-19

Applicant: Cadence Design Systems, Inc.

Inventor： Rajesh Khurana ,  Vivek Chickermane ,  Divyank Mittal ,  Balveer Singh Koranga

IPC: G06F30/30 ,  G01R31/3185

Abstract: Systems, methods, media, and other such embodiments described herein relate to improved operation of test devices which verify circuit operations. One embodiment involves accessing a circuit design comprising a plurality of instances of one or more blocks, where each block of the one or more blocks is associated with a corresponding block test pattern comprising one or more test subpatterns. Each corresponding block test pattern is processed to identify independent test subpatterns, and then each instance is processed to identify each independent test subpattern for the circuit design. Similar types of independent test subpatterns are merged into a circuit design test pattern, such that at least two of the independent test subpatterns associated with the circuit design occupy shared test cycles within the circuit design test pattern.

公开(公告)号：US10761131B1

公开(公告)日：2020-09-01

申请号：US16140701

申请日：2018-09-25

Applicant: CADENCE DESIGN SYSTEMS, INC.

Inventor： Christos Papameletis ,  Brian Edward Foutz ,  Vivek Chickermane ,  Krishna Vijaya Chakravadhanula

IPC: G01R31/28 ,  G01R31/3177 ,  G06F30/398

Abstract: Methods and computer-readable media for testing integrated circuit designs implement a physically efficient scan by optimally balancing and connecting scan segments in a 2-dimensional compression chain architecture. A compression architecture that provides an optimal and balanced configuration of scan segments in 2D compression grids to not only decrease test time, but also to maximize compression efficiency and limit wiring congestion for IC designs that contain complex scan segments facilitates efficient scanning of data by bisecting the elements into balanced partitions of the same target scan length. A segment padding algorithm, followed by a bisecting algorithm and ultimately an element swapping algorithm may be applied to optimally balance and connect scan segments in 2-D compression chains, optimizing an efficient compression architecture which minimizes scan testing resources and time.

公开(公告)号：US10747922B1

公开(公告)日：2020-08-18

申请号：US15956573

申请日：2018-04-18

Applicant: Cadence Design Systems, Inc.

Inventor： Akhil Garg ,  Sahil Jain ,  Vivek Chickermane

IPC: G06F30/33 ,  G01R31/28 ,  G06F30/333

Abstract: A test circuit includes a plurality of codec logic elements arranged in a plurality of annular rings on an integrated circuit, each codec logic element configured to provide test bits to one or more respective scan chain and receive test result bits from the one or more respective scan chain. The test circuit further includes a decompressor logic arranged along at least one annular ring of the plurality of annular rings on the integrated circuit, the decompressor logic configured to provide test bits to at least one codec logic element in each annular ring. The test circuit also includes a compressor logic arranged transversely with respect to the plurality of annular rings on the integrated circuit, the compressor logic configured to receive test result bits from at least one of the plurality of codec logic elements.

公开(公告)号：US09513335B1

公开(公告)日：2016-12-06

申请号：US14738763

申请日：2015-06-12

Applicant: Cadence Design Systems, Inc.

Inventor： Steev Wilcox ,  Brian Edward Foutz ,  Paul Alexander Cunningham ,  Vivek Chickermane ,  Krishna Vijaya Chakravadhanula

IPC: G06F11/22 ,  G06F17/50 ,  G01R31/3177

CPC classification number: G01R31/318547

Abstract: Methods and apparatus for decompressing test data using XOR trees for application to scan chains of a design for test (DFT) integrated circuit in a physically efficient construction are disclosed. Moreover, methods and apparatus for compressing test response data from scan chains in a DFT integrated circuit in a physically efficient construction are disclosed. The XOR tree decompression method may comprise splitting signals at each node of the XOR trees according to distribution logic implemented by a set of XOR gates. The XOR tree compression method may comprise combining signals at each node of the XOR trees according to combination logic implemented by a set of XOR gates.

Abstract translation: 公开了使用XOR树解压缩测试数据的方法和装置，用于在物理上有效的结构中应用于测试（DFT）集成电路设计的扫描链。 此外，公开了用于在物理上有效的结构中的DFT集成电路中的来自扫描链的测试响应数据的压缩方法和装置。 XOR树解压缩方法可以包括根据由一组异或门实现的分布逻辑在XOR树的每个节点处分离信号。 XOR树压缩方法可以包括根据由一组异或门实现的组合逻辑在XOR树的每个节点处组合信号。

公开(公告)号：US09470754B1

公开(公告)日：2016-10-18

申请号：US14737331

申请日：2015-06-11

Applicant: Cadence Design Systems, Inc.

Inventor： Vivek Chickermane ,  Krishna Vijaya Chakravadhanula ,  Brian Edward Foutz ,  Steev Wilcox ,  Paul Alexander Cunningham ,  David George Scott ,  Louis Christopher Milano ,  Dale Edward Meehl

IPC: G01R31/28 ,  G01R31/3177

CPC classification number: G01R31/318335 ,  G01R31/3177 ,  G01R31/318547

Abstract: Systems and methods disclosed herein provide for utilizing extra variables in the decompression equation set of an ATPG process for test patterns requiring an excess number of care bits than can be supported efficiently by the current hardware. An elastic interface is utilized between a tester and a decompressor network (e.g., sequential and combinational decompressors) in order to expand the test pattern length and/or the number of input variables. The systems and methods also provide care bits in early scan cycles of the ATPG process for sequential decompressors starting from a fixed state.

Abstract translation: 本文公开的系统和方法提供了在ATPG过程的解压缩方程组中利用额外的变量，用于需要超过当前硬件有效支持的多余护理位的测试模式。 在测试器和解压缩器网络（例如，顺序和组合解压缩器）之间使用弹性接口，以便扩展测试图案长度和/或输入变量的数量。 这些系统和方法还在ATPG过程的早期扫描周期中为从固定状态开始的顺序解压缩器提供护理位。