公开(公告)号：US20170186784A1

公开(公告)日：2017-06-29

申请号：US15300362

申请日：2015-10-19

Applicant: BOE Technology Group Co., Ltd.

Inventor： Wei Yang ,  Xiang Liu

IPC: H01L27/12 ,  H01L29/66 ,  H01L21/425 ,  H01L29/423 ,  H01L29/786

Abstract: A thin-film transistor (TFT) and a manufacturing method thereof, an array substrate and a manufacturing method thereof, and a display device are disclosed. The manufacturing method of a TFT includes: forming an active layer, a gate electrode, a source electrode and a drain electrode respectively electrically connected with the active layer, and a gate insulating layer disposed between the gate electrode and the active layer, so that the gate electrode, the source electrode and the drain electrode are formed in the same patterning process. The method can reduce the number of masks used in the manufacturing process of the TFT or an array substrate, reduce the technology process, improve the productivity, and reduce the production cost.

公开(公告)号：US09684217B2

公开(公告)日：2017-06-20

申请号：US14771694

申请日：2015-01-04

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiang Liu

IPC: G02F1/1368 ,  H01L21/467 ,  H01L27/12 ,  G02F1/1362 ,  H01L29/786 ,  H01L21/77

CPC classification number: G02F1/1368 ,  G02F1/1362 ,  G02F1/136227 ,  H01L21/467 ,  H01L21/77 ,  H01L27/12 ,  H01L27/1225 ,  H01L27/127 ,  H01L27/1288 ,  H01L29/66969 ,  H01L29/78606 ,  H01L29/7869 ,  H01L29/78693

Abstract: An array substrate, a method for manufacturing the same and a liquid crystal display device are provided. A metal oxide semiconductor layer and an etching stop layer are sequentially formed on a gate insulating layer. One patterning process is performed in the etching stop layer to form a source electrode contact region via hole, a drain electrode contact region via hole and an insulation region. A source-drain electrode layer is formed on the etching stop layer. During a process of performing one patterning process in the source-drain electrode layer to form a source-drain electrode pattern, a portion of the metal oxide semiconductor layer corresponding to the insulation region is removed so that the metal oxide semiconductor layer is disconnected at a position corresponding to the insulation region. The insulation region surrounds the source-drain electrode pattern.

公开(公告)号：US09632382B2

公开(公告)日：2017-04-25

申请号：US14105600

申请日：2013-12-13

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiang Liu

IPC: H01L27/12 ,  H01L29/45 ,  G02F1/1368

CPC classification number: G02F1/1368 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1251 ,  H01L27/127 ,  H01L29/45 ,  H01L29/66969 ,  H01L29/7869

Abstract: The example of present invention provides an array substrate, the method for manufacturing the same, and a liquid crystal display device, wherein the array substrate comprises: a gate electrode, a gate insulating layer, a barrier layer pattern and an active semiconductor layer pattern formed by metal oxide semiconductor which are located on the gate insulating layer, a semiconductor protecting layer which covers the barrier layer pattern and the active semiconductor layer pattern, and has via holes at positions corresponding to the barrier layer pattern and the active semiconductor layer pattern; a data wire, a source electrode and a drain electrode formed by metal Cu, which are located at via holes. Metal Cu is used to form the data wire, the source electrode and the drain electrode, and the metal oxide semiconductor is used as the barrier layer for the metal Cu, and as a result, the diffusion of metal Cu into the layers such as the gate insulating layer etc., is prevented in the manufacturing process of TFT.

公开(公告)号：US09423662B2

公开(公告)日：2016-08-23

申请号：US14420737

申请日：2014-03-24

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiang Liu

IPC: H01L29/06 ,  G02F1/1368 ,  H01L29/786 ,  H01L27/12 ,  G02F1/1362 ,  H01L29/24 ,  H01L29/423 ,  H01L29/16

CPC classification number: G02F1/1368 ,  G02F1/136286 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1244 ,  H01L29/1606 ,  H01L29/24 ,  H01L29/42384 ,  H01L29/78684 ,  H01L29/7869 ,  H01L29/78696

Abstract: The present invention provides a thin film transistor, an array substrate and a display device, relating to the field of display technology, for solving the problem that a source/drain electrode metals and a gate metal may be short-circuited in the manufacturing process of an existing bottom-gate thin film transistor. The thin film transistor of the present invention comprises: a gate formed on a substrate, the gate being connected with a gate line; and a semiconductor layer formed on the gate and the gate line, at least a part of the semiconductor layer extends in the direction parallel to the substrate to exceed the edge of the gate. The array substrate of the present invention comprises the thin film transistor, and the display device comprises the array substrate. The present invention may improve the yield of the bottom-gate thin film transistor.

Abstract translation: 本发明提供一种与显示技术领域相关的薄膜晶体管，阵列基板和显示装置，用于解决源极/漏极金属和栅极金属在制造过程中可能短路的问题 现有的底栅薄膜晶体管。 本发明的薄膜晶体管包括：形成在基板上的栅极，栅极与栅极线连接; 以及形成在栅极和栅极线上的半导体层，半导体层的至少一部分在平行于衬底的方向上延伸超过栅极的边缘。 本发明的阵列基板包括薄膜晶体管，显示装置包括阵列基板。 本发明可以提高底栅薄膜晶体管的产量。

公开(公告)号：US09236405B2

公开(公告)日：2016-01-12

申请号：US13995932

申请日：2012-11-23

Applicant: BOE Technology Group Co., Ltd.

Inventor： Xiang Liu

IPC: H01L27/12 ,  G02F1/1368 ,  H01L29/66 ,  G02F1/1362

CPC classification number: H01L27/127 ,  G02F1/1368 ,  G02F2001/136231 ,  G02F2001/136295 ,  H01L27/1214 ,  H01L27/1288 ,  H01L29/66765

Abstract: An array substrate, a manufacturing method thereof and a display device are provided. In the manufacturing method, the needed patterns can be formed by just three photolithography processes, wherein the semiconductor layer and the etch stop layer are formed by just one photolithography process. The method reduces one photolithography process compared to the method of the state of the art, which forms the pattern of the semiconductor layer and the etch stop layer by two photolithography processes respectively, thereby greatly reducing the manufacturing cost and improving the production efficiency.

Abstract translation: 提供阵列基板，其制造方法和显示装置。 在制造方法中，所需的图案可以仅通过三个光刻工艺形成，其中半导体层和蚀刻停止层仅通过一个光刻工艺形成。 与现有技术的方法相比，该方法减少了一个光刻工艺，其分别通过两个光刻工艺形成半导体层和蚀刻停止层的图案，从而大大降低了制造成本并提高了生产效率。

公开(公告)号：US09190564B2

公开(公告)日：2015-11-17

申请号：US13995122

申请日：2012-11-07

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jing Yang ,  Jianshe Xue ,  Xiang Liu

IPC: H01L21/00 ,  H01L33/08 ,  G02F1/1362 ,  H01L27/12

CPC classification number: H01L33/08 ,  G02F1/1362 ,  H01L27/1288

Abstract: An array substrate and a method for fabricating the same are disclosed. The method for fabricating the array substrate comprises: forming a pattern of a gate electrode (2) and a common electrode (3) on a substrate (1); forming a pattern of a gate insulating layer (4), an active layer (5), a source/drain electrode layer (6) and a first passivation layer (7), wherein the first passivation layer (7) has a via hole and a thin film transistor (TFT) channel window, and the TFT channel window is located above the gate electrode (2); forming a TFT channel and a pixel electrode (9) with slits, wherein the pixel electrode (9) is connected to one of the source/drain electrode (6) through the via hole. The method is not only simple and stable but also improves the TFT quality.

Abstract translation: 公开了阵列基板及其制造方法。 制造阵列基板的方法包括：在基板（1）上形成栅极（2）和公共电极（3）的图案; 形成栅极绝缘层（4），有源层（5），源/漏电极层（6）和第一钝化层（7）的图案，其中第一钝化层（7）具有通孔和 薄膜晶体管（TFT）沟道窗口，TFT沟道窗口位于栅电极（2）的上方; 形成具有狭缝的TFT沟道和像素电极（9），其中，所述像素电极（9）通过所述通孔与所述源极/漏极电极（6）中的一个连接。 该方法不仅简单稳定，而且提高了TFT的质量。

公开(公告)号：US20140103333A1

公开(公告)日：2014-04-17

申请号：US13822480

申请日：2012-12-17

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiang Liu ,  Woobong Lee

IPC: H01L27/12

CPC classification number: H01L27/127 ,  G02F1/1368 ,  H01L27/1225 ,  H01L29/78618 ,  H01L29/78693

Abstract: Embodiments of the present invention provide a thin film transistor array substrate, a method for manufacturing the same, a display panel and a display device. The method for manufacturing the thin film transistor array substrate comprises: sequentially depositing a first metal oxide layer, a second metal oxide layer and a source and drain metal layer, conductivity of the first metal oxide layer being smaller than conductivity of the second metal oxide layer; patterning the first metal oxide layer, the second metal oxide layer and the source and drain metal layer, so as to form an active layer, a buffer layer, a source electrode and a drain electrode, respectively. According to technical solutions of the embodiments of the invention, it is possible that the manufacturing process of the metal oxide TFT array substrate is simplified, and the production cost of products is reduced.

Abstract translation: 本发明的实施例提供一种薄膜晶体管阵列基板，其制造方法，显示面板和显示装置。 制造薄膜晶体管阵列基板的方法包括：依次沉积第一金属氧化物层，第二金属氧化物层和源极和漏极金属层，第一金属氧化物层的导电性小于第二金属氧化物层的导电率 ; 图案化第一金属氧化物层，第二金属氧化物层和源极和漏极金属层，以分别形成有源层，缓冲层，源电极和漏电极。 根据本发明的实施方式的技术方案，可以简化金属氧化物TFT阵列基板的制造工序，降低产品的生产成本。

公开(公告)号：US10663649B2

公开(公告)日：2020-05-26

申请号：US16415189

申请日：2019-05-17

Applicant: HEFEI BOE DISPLAY LIGHTING CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Qiping Zhang ,  Yeshun Xu ,  Xing Wang ,  Xiang Liu ,  Zungan Ling

IPC: F21V8/00

Abstract: Provided are a light guide plate and a method for preparing the same, a backlight module, and a display device. The light guide plate includes a substrate having a first surface and a second surface; and a dot layer arranged on the second surface, in which the dot layer includes magnetic particles, and the first surface is a light exiting surface of the light guide plate.

公开(公告)号：US09917111B2

公开(公告)日：2018-03-13

申请号：US14422829

申请日：2014-05-23

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiang Liu

IPC: H01L27/12 ,  H01L27/32 ,  H01L29/66 ,  H01L23/522 ,  H01L23/52

CPC classification number: H01L27/124 ,  H01L23/5226 ,  H01L27/12 ,  H01L27/1225 ,  H01L29/66969 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present invention belongs to the field of display technology and particularly relates to an electrode lead-out structure, an array substrate and a display device. The electrode lead-out structure comprises a substrate electrode, an isolating layer and an lead-out electrode. The isolating layer covers the substrate electrode to expose a part of region of the substrate electrode through a via formed in the isolating layer, and the lead-out electrode is in contact with the exposed region of the substrate electrode, wherein the lead-out electrode covers the wall and bottom of the via of the isolating layer and extends from an upper edge of the via of the isolating layer along an upper surface of the isolating layer to overlap with the upper layer of the isolating layer.

公开(公告)号：US09525075B2

公开(公告)日：2016-12-20

申请号：US15098398

申请日：2016-04-14

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Xiang Liu

IPC: H01L29/10 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66 ,  H01L27/12

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/1259 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/42384 ,  H01L29/66969 ,  H01L29/78696

Abstract: An array substrate provided according to the present disclosure may include: a base substrate; a gate electrode and a gate insulating layer sequentially formed on the base substrate; a semiconductor layer formed on the base substrate on which the gate insulating layer has been formed; and a source electrode and a drain electrode formed on the base substrate on which the semiconductor layer has been formed. The semiconductor layer may be connected to the source electrode and the drain electrode respectively. A first connection region in which a first connection point is located may be arranged between the semiconductor layer and the source electrode. And a second connection region in which a second connection point is located may be arranged between the semiconductor layer and the drain electrode. A length of a shortest distance on the semiconductor layer from the first connection point to the second connection point may be no less than a reference distance which refers to a longest distance of a straight line between any two points among all points on a perimeter of the gate electrode.

Abstract translation: 根据本公开提供的阵列基板可以包括：基底; 依次形成在所述基底基板上的栅极电极和栅极绝缘层; 形成在已经形成有栅极绝缘层的基底基板上的半导体层; 以及形成在已经形成有半导体层的基底基板上的源电极和漏电极。 半导体层可以分别连接到源电极和漏电极。 第一连接点所在的第一连接区域可以布置在半导体层和源电极之间。 并且其中第二连接点所在的第二连接区域可以布置在半导体层和漏电极之间。 从第一连接点到第二连接点的半导体层上的最短距离的长度可以不小于参考距离，该参考距离是指在距离第二连接点的周长上的所有点中的任何两点之间的直线的最长距离 栅电极。