公开(公告)号：US5227316A

公开(公告)日：1993-07-13

申请号：US744191

申请日：1991-08-12

Applicant: Madhukar Vora ,  Greg Burton ,  Ashok Kapoor

Inventor： Madhukar Vora ,  Greg Burton ,  Ashok Kapoor

IPC: H01L21/285 ,  H01L21/768 ,  H01L21/8249 ,  H01L23/485 ,  H01L23/528 ,  H01L23/532 ,  H01L27/108 ,  H01L27/11

CPC classification number: H01L23/53271 ,  H01L21/28518 ,  H01L21/76877 ,  H01L21/76889 ,  H01L21/8249 ,  H01L23/485 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S148/011 ,  Y10S148/019

Abstract: There is disclosed herein a bipolar transistor structure having a self aligned extended silicide base contact. The contact extends to the position of a base contact window located outside the perimeter of the isolation island on a contact pad formed over the field oxide. This allows the size of the isolation island to be kept smaller and allows a smaller extrinsic base region to be formed. The base contact is formed of titanium and titanium silicide where the titanium/silicide boundary is self aligned with the edge of the device isolation island. The silicide is formed by reacting the titanium which completely covers the exposed epitaxial silicon inside the isolation island. An anisotropically etched oxide sidewall spacer insulates the silicide from the sidewall of the silicide-covered, polysilicon emitter contact.

公开(公告)号：US20080093636A1

公开(公告)日：2008-04-24

申请号：US11962043

申请日：2007-12-20

Applicant: Madhukar Vora ,  Ashok Kapoor

Inventor： Madhukar Vora ,  Ashok Kapoor

IPC: H01L29/80 ,  H01L21/337

CPC classification number: H04L7/0337 ,  H01L21/2257 ,  H01L21/76816 ,  H01L21/76897 ,  H01L29/66901 ,  H01L29/808 ,  H01L2924/0002 ,  H03L7/0812 ,  H04L7/0037 ,  H01L2924/00

Abstract: A scalable device structure and process for forming a normally off JFET with 45 NM linewidths or less. The contacts to the source, drain and gate areas are formed by forming a layer of oxide of a thickness of less than 1000 angstroms, and, preferably 500 angstroms or less on top of the substrate. A nitride layer is formed on top of the oxide layer and holes are etched for the source, drain and gate contacts. A layer of polysilicon is then deposited so as to fill the holes and the polysilicon is polished back to planarize it flush with the nitride layer. The polysilicon contacts are then implanted with the types of impurities necessary for the channel type of the desired transistor and the impurities are driven into the semiconductor substrate below to form source, drain and gate regions.

Abstract translation: 用于形成45 N线宽以下的常闭JFET的可扩展器件结构和工艺。 源极，漏极和栅极区域的触点通过在基板的顶部上形成厚度小于1000埃，优选为500埃或更小的氧化物层来形成。 在氧化物层的顶部形成氮化物层，蚀刻用于源极，漏极和栅极接触的孔。 然后沉积多晶硅层以填充孔，并且将多晶硅抛光回去以使其与氮化物层齐平。 然后将多晶硅触点注入所需晶体管的沟道类型所需的杂质类型，并将杂质驱动到下面的半导体衬底中以形成源极，漏极和栅极区域。

公开(公告)号：US20070229145A1

公开(公告)日：2007-10-04

申请号：US11684466

申请日：2007-03-09

Applicant: Ashok Kapoor ,  Robert Strain ,  Reuven Marko

Inventor： Ashok Kapoor ,  Robert Strain ,  Reuven Marko

IPC: H03K3/01

CPC classification number: H03K19/0963 ,  H01L21/823807 ,  H01L27/0727 ,  H01L27/0921

Abstract: Metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, that are area efficient, and that exhibit improved drive strength and leakage current that are disclosed. A dynamic threshold voltage control scheme is used that does not require a change to existing MOS technology processes. Threshold voltage of the transistor is controlled, such that in the Off state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. The advantages provided by apply to dynamic logic, as well as in the specific well separation imposed by design rules because well potential difference are lower than the supply voltage swing.

Abstract translation: 可在低于1.5V的电压下工作的金属氧化物半导体（MOS）晶体管，其面积效率高，并且表现出改进的驱动强度和漏电流。 使用动态阈值电压控制方案，其不需要改变现有的MOS技术过程。 控制晶体管的阈值电压，使得在关断状态下，晶体管的阈值电压被设置为高，从而将晶体管泄漏保持在较小的值。 动态逻辑提供的优点，以及设计规则施加的具体井分离，因为潜在电位差低于电源电压摆幅。

公开(公告)号：US20060006923A1

公开(公告)日：2006-01-12

申请号：US11029542

申请日：2005-01-04

Applicant: Ashok Kapoor

Inventor： Ashok Kapoor

IPC: H03K3/01

CPC classification number: H03K19/0005 ,  H01L27/0629 ,  H01L2924/0002 ,  H03K19/0016 ,  H03K19/00361 ,  H01L2924/00

Abstract: An apparatus and method for manufacturing metal-oxide semiconductor (MOS) transistors that are operable at voltages below 1.5V, which MOS transistors are area efficient, and where the drive strength and leakage current of the MOS transistors is improved. The invention uses a dynamic threshold voltage control scheme that does not require a change to the existing MOS technology process. The invention provides a technique that controls the threshold voltage of the transistor. In the OFF state, the threshold voltage of the transistor is set high, keeping the transistor leakage to a small value. In the ON state, the threshold voltage is set to a low value, resulting in increased drive strength. The invention is particularly useful in MOS technology for both bulk and silicon on insulator (SOI) CMOS.

公开(公告)号：US6121794A

公开(公告)日：2000-09-19

申请号：US199885

申请日：1998-11-24

Applicant: Ashok Kapoor

Inventor： Ashok Kapoor

IPC: H01L27/092 ,  H03K19/0175 ,  H01L27/082

CPC classification number: H03K19/017518 ,  H01L27/092

Abstract: A CMOS buffer circuit isolates the low voltage CMOS logic gate from high voltage components on the chip and in the environment. The CMOS buffer circuit uses high voltage npn bipolar transistors with at least two P implants in the N- well serving as the base. The processing of the npn bipolar transistors uses an extra mask for the additional P implant, but advantageously does not require a thicker oxide growth. A CMOS output buffer circuit includes two high voltage npn bipolar transistors connected between the high voltage supply, e.g., 5.0 volts, and ground. The two bipolar transistors are driven by complementary signals generated by an inverter circuit or an emitter coupled logic circuit. The inverter circuit or emitter coupled logic circuit receive an input signal from the CMOS logic gate, which is connected between the low voltage supply, e.g., 1.8 to 3.3 volts, and ground. A CMOS input buffer circuit uses a transistor--transistor logic circuit configuration connected between the high voltage supply and ground to drive the CMOS logic gate, which again is connected between the low voltage supply and ground. A resistor connected between the input terminal of the CMOS logic gate and ground is configured such that the voltage across it exceeds the switching threshold of the CMOS logic gate.

Abstract translation: CMOS缓冲电路将低压CMOS逻辑门与芯片和环境中的高电压组件隔离开来。 CMOS缓冲电路使用高电压npn双极晶体管，其中N阱中至少有两个P种植入物作为基极。 npn双极晶体管的处理使用额外的掩模用于附加的P植入物，但是有利地不需要更厚的氧化物生长。 CMOS输出缓冲电路包括连接在例如5.0伏特的高压电源和地之间的两个高电压npn双极晶体管。 两个双极晶体管由逆变器电路或发射极耦合逻辑电路产生的互补信号驱动。 逆变器电路或发射极耦合逻辑电路接收来自CMOS逻辑门的输入信号，其连接在低电压电源（例如1.8至3.3伏特）和地之间。 CMOS输入缓冲电路使用连接在高压电源和地之间的晶体管晶体管逻辑电路配置来驱动CMOS逻辑门，CMOS逻辑门又连接在低压电源和地之间。 连接在CMOS逻辑门和地的输入端之间的电阻被配置成使得它两端的电压超过了CMOS逻辑门的切换阈值。

公开(公告)号：US5761110A

公开(公告)日：1998-06-02

申请号：US779992

申请日：1996-12-23

Applicant: V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond T. Leung ,  Alex Owens ,  Thomas R. Wik

Inventor： V. Swamy Irrinki ,  Ashok Kapoor ,  Raymond T. Leung ,  Alex Owens ,  Thomas R. Wik

IPC: G11C11/56 ,  G11C17/14

CPC classification number: G11C11/56

Abstract: A system and process which enables storage of more than two logic states in a memory cell. In one embodiment, a programmable resistor is coupled in series with a transistor between a supply voltage and a data read line. When an access signal is asserted, the transistor provides a conductive path, and a voltage drop is sustained by the programmable resistor. The programmable resistor has a resistance which is set during a programming step to one of a plurality of values by passing a heating current through the programmable resistor for one of a corresponding plurality of predetermined lengths of time. When the access signal is asserted, the voltage drop sustained across the programmable resistor is indicative of the stored logic state. An analog-to-digital (A/D) converter is coupled to the data read line so as to sense the voltage drop and determine the state represented. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit.

Abstract translation: 一种允许在存储器单元中存储两个以上逻辑状态的系统和过程。 在一个实施例中，可编程电阻器与电源电压和数据读取线之间的晶体管串联耦合。 当访问信号被断言时，晶体管提供导电路径，并且由可编程电阻器维持电压降。 可编程电阻器具有在编程步骤期间通过使加热电流通过可编程电阻器的多个预定时间段中的一个来设定的电阻。 当访问信号被断言时，跨可编程电阻器持续的电压降指示存储的逻辑状态。 模数（A / D）转换器耦合到数据读取线，以便感测电压降并确定所表示的状态。 由于附加逻辑状态可用于表示附加信息位，所以该存储器电路增加了每个存储单元可以存储的位数，由此增加存储密度并降低每位的成本。

公开(公告)号：US5644152A

公开(公告)日：1997-07-01

申请号：US462653

申请日：1995-06-05

Applicant: Michael D. Rostoker ,  Ashok Kapoor

Inventor： Michael D. Rostoker ,  Ashok Kapoor

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L29/423 ,  H01L29/788 ,  H01L29/161 ,  H01L29/34

CPC classification number: H01L29/66825 ,  H01L21/2807 ,  H01L27/11517 ,  H01L29/42324 ,  Y10S148/059

Abstract: A conductive member is described with a surface of controlled roughness thereon which is useful in the construction of an integrated circuit structure. In a preferred embodiment, the conductive member is formed using a mixture of germanium and silicon which is then oxidized, resulting in the formation of a roughened surface on the germanium/silicon conductive member due to the difference in the respective rates of oxidation of the germanium and silicon. After oxidation of the conductive member, the oxide layer may be removed, leaving the toughened surface on the germanium/silicon conductive member. When an integrated circuit structure such as an EPROM is to be formed using this conductive member with a roughened surface, a further layer of oxide is then deposited over the roughened surface followed by deposition of a second layer of conductive material such as polysilicon or a germanium/silicon mixture, from which the control gate will be formed. A further oxide layer may then be formed over the second conductive layer followed by a patterning step to respectively form the floating gate (from the germanium/silicon layer) and the control gate from the second conductive layer.

Abstract translation: 描述了导电构件，其上具有受控粗糙度的表面，其可用于集成电路结构的构造。 在优选实施例中，使用锗和硅的混合物形成导电构件，然后将其氧化，导致在锗/硅导电构件上形成粗糙表面，这是由于锗的氧化速率的差异 和硅。 在氧化导电部件之后，可以去除氧化物层，留下锗/硅导电部件上的增韧表面。 当使用具有粗糙表面的导电部件形成诸如EPROM的集成电路结构时，然后在粗糙表面上沉积另外的氧化物层，随后沉积第二层导电材料，例如多晶硅或锗 /硅混合物，从其形成控制栅极。 然后可以在第二导电层上形成另外的氧化物层，接着形成图案化步骤以分别从第二导电层形成浮栅（来自锗/硅层）和控制栅极。