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    GRADED DOPING IN POWER DEVICES
    21.
    发明申请
    GRADED DOPING IN POWER DEVICES 有权

    公开(公告)号：US20220254886A1

    公开(公告)日：2022-08-11

    申请号：US17169916

    申请日：2021-02-08

    Applicant: Applied Materials, Inc.

    Inventor： Ashish Pal ,  El Mehdi Bazizi ,  Siddarth Krishnan ,  Xing Chen ,  Lan Yu ,  Tyler Sherwood

    IPC: H01L29/36 ,  H01L29/872 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L21/3065 ,  H01L29/66

    Abstract: Exemplary methods of forming a semiconductor structure may include forming a doped silicon layer on a semiconductor substrate. A level of doping may be increased at an increasing distance from the semiconductor substrate. The methods may include etching the doped silicon layer to define a trench extending to the semiconductor substrate. The doped silicon layer may define a sloping sidewall of the trench. The trench may be characterized by a depth of greater than or about 30 μm. The methods may include lining the trench with a first oxide material. The methods may include depositing a second oxide material within the trench. The methods may include forming a contact to produce a power device.

    DEEP TRENCH INTEGRATION PROCESSES AND DEVICES
    22.
    发明申请
    DEEP TRENCH INTEGRATION PROCESSES AND DEVICES 有权

    公开(公告)号：US20220165610A1

    公开(公告)日：2022-05-26

    申请号：US16953567

    申请日：2020-11-20

    Applicant: Applied Materials, Inc.

    Inventor： Lan Yu ,  Tyler Sherwood ,  Michael Chudzik ,  Siddarth Krishnan

    IPC: H01L21/768 ,  H01L21/762 ,  H01L29/06

    Abstract: Exemplary methods of forming a semiconductor device may include etching a trench from a first surface of a semiconductor substrate to a first depth within the semiconductor substrate. The trench may be characterized by a first width through the first depth. The methods may include forming a liner along sidewalls of the trench. The methods may include etching the trench to a second depth at least ten times greater than the first depth. The trench may be characterized by a second width through the second depth. The methods may include filling the trench with a dielectric material. A seam formed in the dielectric material may be maintained below the first depth.

    METHOD FOR LCOS DBR MULTILAYER STACK PROTECTION VIA SACRIFICIAL HARDMASK FOR RIE AND CMP PROCESSES
    23.
    发明申请
    METHOD FOR LCOS DBR MULTILAYER STACK PROTECTION VIA SACRIFICIAL HARDMASK FOR RIE AND CMP PROCESSES 有权

    公开(公告)号：US20220163846A1

    公开(公告)日：2022-05-26

    申请号：US17100422

    申请日：2020-11-20

    Applicant: Applied Materials, Inc.

    Inventor： Lan Yu ,  Benjamin D. Briggs ,  Tyler Sherwood ,  Raghav Sreenivasan

    IPC: G02F1/1335 ,  H01L21/768 ,  G02F1/1362 ,  H01L23/522

    Abstract: Processing methods may be performed to forming a pixel material in a semiconductor structure. The methods may include forming a sacrificial hardmask overlying an uppermost layer of an optical stack of the semiconductor structure, the uppermost layer having a thickness. The methods may include forming a via through the sacrificial hardmask in the optical stack by a first etch process unselective to a metal layer of the semiconductor structure. The methods may include filling the via with a fill material, wherein a portion of the fill material extends over the sacrificial hardmask and contacts the metal layer. The methods may include removing a portion of the fill material external to the via by a removal process selective to the fill material. The methods may also include removing the sacrificial hardmask by a second etch process selective to the sacrificial hardmask while maintaining the thickness of the uppermost layer.

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