公开(公告)号：US09601431B2

公开(公告)日：2017-03-21

申请号：US14173807

申请日：2014-02-05

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Mehul B. Naik ,  Yong Cao ,  Mei-yee Shek ,  Yana Cheng ,  Sree Rangasai V. Kesapragada

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L21/285

CPC classification number: H01L23/53238 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure for use in semiconductor devices and a method for fabricating the same is described. The method includes positioning a substrate in a vacuum processing chamber. The substrate has an exposed copper surface and an exposed low-k dielectric surface. A metal layer is formed over the copper surface but not over the low-k dielectric surface. A metal-based dielectric layer is formed over the metal layer and the low-k dielectric layer.

公开(公告)号：US09368448B2

公开(公告)日：2016-06-14

申请号：US14268727

申请日：2014-05-02

Applicant: Applied Materials, Inc.

Inventor： Yihong Chen ,  Abhijit Basu Mallick ,  Mehul B. Naik ,  Srinivas D. Nemani

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/53238 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76879 ,  H01L23/5283 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method is provided for forming an interconnect structure for use in semiconductor devices. The method starts with forming a low-k bulk dielectric layer on a substrate and then forming a trench in the low-k bulk dielectric layer. A liner layer is formed on the low-k bulk dielectric layer being deposited conformally to the trench. A copper layer is formed on the liner layer filling the trench. Portions of the copper layer and liner layer are removed to form an upper surface of the low-k bulk dielectric layer, the liner layer, and the copper layer. A metal containing dielectric layer is formed on the upper surface of the low-k bulk dielectric layer, the liner layer, and the copper layer.

Abstract translation: 提供一种用于形成用于半导体器件的互连结构的方法。 该方法首先在衬底上形成低k体积电介质层，然后在低k体电介质层中形成沟槽。 衬底层形成在与沟槽共形沉积的低k体积电介质层上。 在填充沟槽的衬垫层上形成铜层。 去除部分铜层和衬层以形成低k体电介质层，衬里层和铜层的上表面。 在低k体电介质层，衬垫层和铜层的上表面上形成含金属的电介质层。

公开(公告)号：US09269563B2

公开(公告)日：2016-02-23

申请号：US14298102

申请日：2014-06-06

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Mehul B. Naik

IPC: H01L21/02 ,  H01L23/00 ,  H01L21/033

CPC classification number: H01L21/02063 ,  H01J37/321 ,  H01J37/32477 ,  H01J37/32642 ,  H01J37/32715 ,  H01L21/0337 ,  H01L21/31122 ,  H01L21/31138 ,  H01L21/76808 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods and apparatuses for forming a dual damascene structure utilizing a selective protection process to protect vias and/or trenches in the dual damascene structure while removing a hardmask layer from the dual damascene structure. In one embodiment, a method for removing a patterned hardmask layer from a substrate includes forming an organic polymer material on a dual damascene structure that exposes substantially a patterned hardmask layer disposed on an upper surface of the dual damascene structure, removing the patterned hardmask layer on the substrate, and removing the organic polymer material from the substrate.

Abstract translation: 用于形成双镶嵌结构的方法和装置，其利用选择性保护过程来保护双镶嵌结构中的通孔和/或沟槽，同时从双镶嵌结构去除硬掩模层。 在一个实施例中，用于从衬底去除图案化硬掩模层的方法包括在双镶嵌结构上形成有机聚合物材料，其暴露基本上设置在双镶嵌结构的上表面上的图案化硬掩模层， 并且从衬底去除有机聚合物材料。

公开(公告)号：US11373903B2

公开(公告)日：2022-06-28

申请号：US15722639

申请日：2017-10-02

Applicant: Applied Materials, Inc.

Inventor： Mehul B. Naik ,  Zhiyuan Wu

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/285

Abstract: Embodiments of the present disclosure are related to improved methods for forming an interconnect structure in a substrate. In one implementation, the method includes providing a substrate comprising a metal region and a dielectric region surrounding the metal region, selectively forming a cobalt-containing alloy cap layer on the metal region by exposing the substrate to a first precursor and a second precursor, the first precursor and the second precursor are selected from a group consisting of an aluminum-containing precursor, a cobalt-containing precursor, a ruthenium-containing precursor, a manganese-containing precursor, and a tungsten-containing precursor, wherein the first precursor is different from the second precursor.

公开(公告)号：US10957533B2

公开(公告)日：2021-03-23

申请号：US16656018

申请日：2019-10-17

Applicant: Applied Materials, Inc.

Inventor： Hao Jiang ,  He Ren ,  Hao Chen ,  Mehul B. Naik

IPC: H01L21/02 ,  H01L21/30 ,  H01L21/477 ,  H01L21/3213 ,  H01L21/67

Abstract: Embodiments of the present disclosure provide methods and apparatus for forming and patterning features in a film stack disposed on a substrate. In one embodiment, a method for patterning a conductive layer on a substrate includes supplying a gas mixture comprising a chlorine containing gas at a first flow rate to etch a first conductive layer disposed on the substrate, lowing the chlorine containing gas in the first gas mixture to a second flow rate lower than the first flow rate to continue etching the first conductive layer, and increasing the chlorine containing gas in the first gas mixture to a third flow rate greater than the second flow rate to remove the first conductive layer from the substrate.

公开(公告)号：US10651043B2

公开(公告)日：2020-05-12

申请号：US16544349

申请日：2019-08-19

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Minrui Yu ,  Mehul B. Naik

IPC: H01L23/48 ,  H01L21/285 ,  H01L21/67 ,  H01L23/532 ,  H01L21/768 ,  C23C14/06 ,  C23C14/34 ,  C23C14/35 ,  H01J37/34 ,  H01L21/3205

Abstract: Methods for depositing a low resistivity nickel silicide layer used in forming an interconnect and electronic devices formed using the methods are described herein. In one embodiment, a method for depositing a layer includes positioning a substrate on a substrate support in a processing chamber, the processing chamber having a nickel target and a silicon target disposed therein, the substrate facing portions of the nickel target and the silicon target each having an angle of between about 10 degrees and about 50 degrees from the target facing surface of the substrate, flowing a gas into the processing chamber, applying an RF power to the nickel target and concurrently applying a DC power to the silicon target, concurrently sputtering silicon and nickel from the silicon and nickel targets, respectively, and depositing a NixSi1-x layer on the substrate, where x is between about 0.01 and about 0.99.

公开(公告)号：US10256144B2

公开(公告)日：2019-04-09

申请号：US15498024

申请日：2017-04-26

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Feiyue Ma ,  Yu Lei ,  Kai Wu ,  Mehul B. Naik ,  Zhiyuan Wu ,  Vikash Banthia ,  Hua Al

IPC: H01L21/4763 ,  H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  H01L23/522

Abstract: Embodiments of the present disclosure generally relate an interconnect formed on a substrate and a method of forming the interconnect thereon. In an embodiment, a via and trench in a stack formed on the substrate. A bottom of the via is pre-treated using a first pre-treatment procedure. A sidewall of the via is pre-treated using a second pre-treatment procedure. A first metal fill material of a first type is deposited on the stack, in the via. A second metal fill material of a second type is deposited on the stack, in the trench.

公开(公告)号：US10170299B2

公开(公告)日：2019-01-01

申请号：US15186436

申请日：2016-06-18

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Mehul B. Naik ,  Yong Cao ,  Yana Cheng ,  Weifeng Ye

IPC: H01L21/02 ,  H01L21/768

Abstract: The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.

公开(公告)号：US10049927B2

公开(公告)日：2018-08-14

申请号：US15332737

申请日：2016-10-24

Applicant: Applied Materials, Inc.

Inventor： Bencherki Mebarki ,  Sean Kang ,  Keith Tatseun Wong ,  He Ren ,  Mehul B. Naik ,  Ellie Y. Yieh ,  Srinivas D. Nemani

IPC: H01L21/76 ,  H01L21/768 ,  H01L23/532

Abstract: Aspects of the disclosure include methods of treating a substrate to remove one or more of voids, seams, and grain boundaries from interconnects formed on the substrate. The method includes heating the substrate in an environment pressurized at supra-atmospheric pressure. In one example, the substrate may be heated in a hydrogen-containing atmosphere.

公开(公告)号：US10008448B2

公开(公告)日：2018-06-26

申请号：US15439145

申请日：2017-02-22

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Mehul B. Naik ,  Yong Cao ,  Mei-yee Shek

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/02178 ,  H01L21/02266 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/7685 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure for use in semiconductor devices and a method for fabricating the same is described. The method includes positioning a substrate in a vacuum processing chamber, wherein the substrate comprises a copper layer having an exposed surface and a low-k dielectric layer having an exposed surface, forming a metal layer over the exposed surface of the copper layer, wherein the exposed surface of the low-k dielectric layer is free from the metal layer, and forming a metal-based dielectric layer over the metal layer and over at least part of the exposed low-k dielectric surface, wherein the metal-based dielectric layer comprises an aluminum compound.