公开(公告)号：US20220028709A1

公开(公告)日：2022-01-27

申请号：US16938517

申请日：2020-07-24

Applicant: Applied Materials, Inc.

Inventor： Kurtis LESCHKIES ,  Jeffrey L. FRANKLIN ,  Wei-Sheng LEI ,  Steven VERHAVERBEKE ,  Jean DELMAS ,  Han-Wen CHEN ,  Giback PARK

IPC: H01L21/67 ,  H01L21/48 ,  B23K26/382 ,  B23K26/0622

Abstract: The present disclosure relates to systems and methods for fabricating semiconductor packages, and more particularly, for forming features in semiconductor packages by laser ablation. In one embodiment, the laser systems and methods described herein can be utilized to pattern a substrate to be utilized as a package frame for a semiconductor package having one or more interconnections formed therethrough and/or one or more semiconductor dies disposed therein. The laser systems described herein can produce tunable laser beams for forming features in a substrate or other package structure. Specifically, frequency, pulse width, pulse shape, and pulse energy of laser beams are tunable based on desired sizes of patterned features and on the material in which the patterned features are formed. The adjustability of the laser beams enables rapid and accurate formation of features in semiconductor substrates and packages with controlled depth and topography.

公开(公告)号：US20210257289A1

公开(公告)日：2021-08-19

申请号：US17227837

申请日：2021-04-12

Applicant: Applied Materials, Inc.

Inventor： Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Giback PARK ,  Kyuil CHO ,  Kurtis LESCHKIES ,  Roman GOUK ,  Chintan BUCH ,  Vincent DICAPRIO ,  Bernhard STONAS ,  Jean DELMAS

IPC: H01L23/498 ,  H01L23/14 ,  H01L21/48

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

公开(公告)号：US20210249345A1

公开(公告)日：2021-08-12

申请号：US17227867

申请日：2021-04-12

Applicant: Applied Materials, Inc.

Inventor： Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Giback PARK ,  Kyuil CHO ,  Kurtis LESCHKIES ,  Roman GOUK ,  Chintan BUCH ,  Vincent DICAPRIO ,  Bernhard STONAS ,  Jean DELMAS

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/14

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

公开(公告)号：US20210159158A1

公开(公告)日：2021-05-27

申请号：US16698680

申请日：2019-11-27

Applicant: Applied Materials, Inc.

Inventor： Han-Wen CHEN ,  Steven VERHAVERBEKE ,  Giback PARK ,  Kyuil CHO ,  Kurtis LESCHKIES ,  Roman GOUK ,  Chintan BUCH ,  Vincent DICAPRIO

IPC: H01L23/498 ,  H01L23/14 ,  H01L21/48

Abstract: The present disclosure relates to semiconductor core assemblies and methods of forming the same. The semiconductor core assemblies described herein may be utilized to form semiconductor package assemblies, PCB assemblies, PCB spacer assemblies, chip carrier assemblies, intermediate carrier assemblies (e.g., for graphics cards), and the like. In one embodiment, a silicon substrate core is structured by direct laser patterning. One or more conductive interconnections are formed in the substrate core and one or more redistribution layers are formed on surfaces thereof. The silicon substrate core may thereafter be utilized as a core structure for a semiconductor package, PCB, PCB spacer, chip carrier, intermediate carrier, or the like.

公开(公告)号：US20200161178A1

公开(公告)日：2020-05-21

申请号：US16675385

申请日：2019-11-06

Applicant: Applied Materials, Inc.

Inventor： Shishi JIANG ,  Kurtis LESCHKIES ,  Pramit MANNA ,  Abhijit MALLICK

IPC: H01L21/768 ,  H01L21/02

Abstract: Embodiments described herein relate to methods of seam-free gapfilling and seam healing that can be carried out using a chamber operable to maintain a supra-atmospheric pressure (e.g., a pressure greater than atmospheric pressure). One embodiment includes positioning a substrate having one or more features formed in a surface of the substrate in a process chamber and exposing the one or more features of the substrate to at least one precursor at a pressure of about 1 bar or greater. Another embodiment includes positioning a substrate having one or more features formed in a surface of the substrate in a process chamber. Each of the one or more features has seams of a material. The seams of the material are exposed to at least one precursor at a pressure of about 1 bar or greater.

公开(公告)号：US20190237345A1

公开(公告)日：2019-08-01

申请号：US16378140

申请日：2019-04-08

Applicant: Applied Materials, Inc.

Inventor： Jean DELMAS ,  Steven VERHAVERBEKE ,  Kurtis LESCHKIES

IPC: H01L21/67 ,  H01L21/677 ,  F27B9/36 ,  H01L21/324

CPC classification number: H01L21/67109 ,  F27B9/36 ,  H01L21/324 ,  H01L21/67017 ,  H01L21/6719 ,  H01L21/67248 ,  H01L21/67748 ,  H01L21/67754

Abstract: Embodiments of the disclosure relate to an apparatus and method for annealing one or more semiconductor substrates. In one embodiment, a processing chamber is disclosed. The processing chamber includes a chamber body enclosing an internal volume, a substrate support disposed in the internal volume and configured to support a substrate during processing, a gas panel configured to provide a processing fluid into the internal volume, and a temperature-controlled fluid circuit configured to maintain the processing fluid at a temperature above a condensation point of the processing fluid. The temperature-controlled fluid circuit includes a gas conduit fluidly coupled to a port on the chamber body at a first end and to the gas panel at a second end.

公开(公告)号：US20190189435A1

公开(公告)日：2019-06-20

申请号：US16201095

申请日：2018-11-27

Applicant: Applied Materials, Inc.

Inventor： Shishi JIANG ,  Kurtis LESCHKIES ,  Pramit MANNA ,  Abhijit Basu MALLICK ,  Steven VERHAVERBEKE

IPC: H01L21/02 ,  C23C8/10

Abstract: Implementations described herein generally relate to methods for forming a low-k dielectric material on a semiconductor substrate. More specifically, implementations described herein relate to methods of forming a silicon oxide film at high pressure and low temperatures. In one implementation, a method of forming a silicon oxide film is provided. The method comprises loading a substrate having a silicon-containing film formed thereon into a processing region of a high-pressure vessel. The method further comprises forming a silicon oxide film on the silicon-containing film. Forming the silicon oxide film on the silicon-containing film comprises exposing the silicon-containing film to a processing gas comprising steam at a pressure greater than about 1 bar and maintaining the high-pressure vessel at a temperature between about 100 degrees Celsius and about 500 degrees Celsius.

公开(公告)号：US20140264354A1

公开(公告)日：2014-09-18

申请号：US14203433

申请日：2014-03-10

Applicant: APPLIED MATERIALS, INC.

Inventor： Kurtis LESCHKIES ,  Steven VERHAVERBEKE ,  Robert VISSER ,  John M. WHITE ,  Yan YE ,  Dong-Kil YIM

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L29/4908

Abstract: The present invention generally relates to a thin film semiconductor device having a buffer layer formed between the semiconductor layer and one or more layers. In one embodiment, a thin film semiconductor device includes a semiconductor layer having a first work function and a first electron affinity level, a buffer layer having a second work function greater than the first work function and a second electron affinity level that is less than the first electron affinity level; and a gate dielectric layer having a third work function less than the second work function and a third electron affinity level that is greater than the second electron affinity level.

Abstract translation: 本发明一般涉及一种在半导体层与一层或多层之间形成缓冲层的薄膜半导体器件。 在一个实施例中，薄膜半导体器件包括具有第一功函数和第一电子亲和度的半导体层，具有大于第一功函数的第二功函数的缓冲层和小于第一功函数的第二电子亲和度 第一电子亲和力水平; 以及具有小于第二功函数的第三功函数和大于第二电子亲和度的第三电子亲和度的栅介质层。

公开(公告)号：US20130102110A1

公开(公告)日：2013-04-25

申请号：US13656485

申请日：2012-10-19

Applicant: Applied Materials, Inc.

Inventor： Kurtis LESCHKIES ,  Steven VERHAVERBEKE ,  Robert VISSER

IPC: H01L31/18

CPC classification number: H01L31/022425 ,  H01L31/03921 ,  Y02E10/50

Abstract: The present invention generally includes an apparatus and process of forming a conductive layer on a surface of a host substrate, which can be directly used to form a portion of an electronic device. More specifically, one or more of the embodiments disclosed herein include a process of forming a conductive layer on a surface of a substrate using an electrospinning type deposition process. Embodiments of the conductive layer forming process described herein can be used to reduce the number of processing steps required to form the conductive layer, improve the electrical properties of the formed conductive layer and reduce the conductive layer formation process complexity over current state-of-the-art conductive layer formation techniques. Typical electronic device formation processes that can benefit from one or more of the embodiments described herein include, but are not limited to processes used to form solar cells, electronic visual display devices and touchscreen type technologies.

Abstract translation: 本发明通常包括在主基板的表面上形成导电层的装置和工艺，其可以直接用于形成电子器件的一部分。 更具体地，本文公开的一个或多个实施例包括使用静电纺丝型沉积工艺在基板的表面上形成导电层的工艺。 本文所述的导电层形成方法的实施方案可用于减少形成导电层所需的处理步骤的数量，改善所形成的导电层的电性能，并降低导电层形成工艺的复杂性，超过目前的状态 - 导电层形成技术。 可以受益于本文所述的一个或多个实施方案的典型的电子器件形成方法包括但不限于用于形成太阳能电池的方法，电子视觉显示装置和触摸屏型技术。