知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

47 records (took 0.022 seconds)

    Performance State Selection for Low Activity Scenarios
    21.
    发明申请
    Performance State Selection for Low Activity Scenarios 有权
    低活动情景下的绩效状态选择

    公开(公告)号：US20160306406A1

    公开(公告)日：2016-10-20

    申请号：US14846058

    申请日：2015-09-04

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Alexander J. Branover ,  Adam N.C. Clark ,  Ashish Jain ,  Sridhar V. Gada

    IPC: G06F1/32

    CPC classification number: G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/329 ,  G06F1/3296 ,  G06F9/5094 ,  Y02D10/126 ,  Y02D10/172 ,  Y02D10/24 ,  Y02D50/20

    Abstract: A power management controller tracks the idle state of a compute unit and compares the tracked idle state with a first threshold. If the tracked idle state is above the first threshold a power state of the compute unit is limited to a low power state so that the power state does not rise due to activity that occurs in low utilization scenarios. The tracked idle state is compared to a second threshold and if the tracked idle state is below the second threshold, indicating that the compute unit is not in a low utilization scenario, a limit on the power state is removed and the power state of the compute unit is allowed to rise.

    Abstract translation: 电力管理控制器跟踪计算单元的空闲状态，并将跟踪的空闲状态与第一阈值进行比较。 如果跟踪的空闲状态高于第一阈值，则计算单元的功率状态被限制为低功率状态，使得由于在低利用场景中发生的活动而导致功率状态不上升。 将跟踪的空闲状态与第二阈值进行比较，并且如果跟踪的空闲状态低于第二阈值，则指示计算单元不处于低利用率场景中，则去除功率状态的限制，并且计算的功率状态 单位被允许上升。

    DYNAMIC REALLOCATION OF DISPLAY MEMORY BANDWIDTH BASED ON SYSTEM STATE
    22.
    发明申请
    DYNAMIC REALLOCATION OF DISPLAY MEMORY BANDWIDTH BASED ON SYSTEM STATE 有权

    公开(公告)号：US20240403242A1

    公开(公告)日：2024-12-05

    申请号：US18327813

    申请日：2023-06-01

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Ashish Jain ,  Gia Tung Phan ,  Shang Yang

    IPC: G06F13/16 ,  G06F13/18

    Abstract: An apparatus and method for efficiently managing memory bandwidth within a communication fabric. A computing system includes multiple clients, a display controller, and a communication fabric that transfers data between the multiple clients, the display controller, and a memory subsystem. A control circuit with power management circuitry determines that one or more conditions are satisfied for changing a power-performance state (P-state) of the memory subsystem. The control circuit asserts indications on a sideband interface specifying to the communication fabric that the display controller is to have an increased bandwidth of data transfer between the display controller and the memory subsystem. Using the increased bandwidth provided by the communication fabric, the display controller prefetches display data from a frame buffer of the memory subsystem prior to the P-state change. Afterward, the memory subsystem performs the P-state change and the corresponding training of the memory interface.

    Frequency/State Based Power Management Thresholds
    24.
    发明公开
    Frequency/State Based Power Management Thresholds 审中-公开

    公开(公告)号：US20240111351A1

    公开(公告)日：2024-04-04

    申请号：US17936740

    申请日：2022-09-29

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Ashish Jain ,  Shang Yang

    IPC: G06F1/3206

    CPC classification number: G06F1/3206

    Abstract: A system and method for determining power-performance state transition thresholds in a computing system. A processor comprises several functional blocks and a power manager. Each of the functional blocks produces data corresponding to an activity level associated with the respective functional block. The power manager determines activity levels of the functional blocks and compares the activity level of a given functional block to a threshold to determine if a power-performance state (P-state) transition is indicated. The threshold is determined in part on a current P-state of the given functional block. When the current P-state of the given functional block is relatively high, the threshold activity level to transition to a higher P-state is higher than it would be if the current P-state were relatively low. The power manager is further configured to determine the thresholds based in part on one or more of a type of circuit being monitored and a type of workload being executed.

    BOOSTING THE OPERATING POINT OF A PROCESSING DEVICE FOR NEW USER ACTIVITIES
    26.
    发明申请
    BOOSTING THE OPERATING POINT OF A PROCESSING DEVICE FOR NEW USER ACTIVITIES 审中-公开
    促进新用户活动的处理设备的操作要点

    公开(公告)号：US20150193259A1

    公开(公告)日：2015-07-09

    申请号：US14147470

    申请日：2014-01-03

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Ashish Jain ,  Alexander J. Branover

    IPC: G06F9/46

    CPC classification number: G06F9/4893 ,  G06F1/3206 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/24

    Abstract: A processing system detects user activities on one or more processing units. In response, an operating point (operating frequency or an operating voltage) of the processing unit handing the user activity is increased at the processing unit. Battery power may be conserved in some processing systems by limiting the increase in the operating point to a time interval and reducing the operating frequency or the operating voltage to a previous value after the time interval has elapsed.

    Abstract translation: 处理系统检测一个或多个处理单元上的用户活动。 作为响应，在处理单元处增加处理单元处理用户活动的操作点（操作频率或工作电压）。 在一些处理系统中，通过将工作点的增加限制到时间间隔并且在经过时间间隔之后将工作频率或工作电压降低到先前值，可以节省电池功率。

    BALANCED THROUGHPUT OF REPLICATED PARTITIONS IN PRESENCE OF INOPERABLE COMPUTATIONAL UNITS
    27.
    发明公开
    BALANCED THROUGHPUT OF REPLICATED PARTITIONS IN PRESENCE OF INOPERABLE COMPUTATIONAL UNITS 审中-公开

    公开(公告)号：US20230409392A1

    公开(公告)日：2023-12-21

    申请号：US17844558

    申请日：2022-06-20

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Ashish Jain ,  Sriram Sundaram ,  Christopher Allan Poirier ,  Samuel D. Naffziger

    IPC: G06F9/48 ,  G06F1/26

    CPC classification number: G06F9/4893 ,  G06F1/26

    Abstract: An apparatus and method for efficiently managing balanced performance among replicated partitions of an integrated circuit despite loss of functionality due to manufacturing defects. A processing unit includes at least two replicated partitions, each assigned to operation parameters of a respective power domain. The partitions include multiple compute units. The compute units include multiple lanes of execution. Due to a variety of types of manufacturing defects, one or more of the partitions of the processing unit has less than a predetermined number of operational compute units. To balance the throughput of the multiple partitions, a power manager generates both static and dynamic scaling factors based on at least the corresponding number of operational compute units. Using these scaling factors, the power manager adjusts the operation parameters of power domains for the partitions relative to one another.

    Selection of an operating point of a memory physical layer interface and a memory controller based on memory bandwidth utilization
    29.
    发明授权
    Selection of an operating point of a memory physical layer interface and a memory controller based on memory bandwidth utilization 有权
    基于存储器带宽利用率选择存储器物理层接口的操作点和存储器控制器

    公开(公告)号：US09298243B2

    公开(公告)日：2016-03-29

    申请号：US13932682

    申请日：2013-07-01

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Ashish Jain ,  Alexander J. Branover

    IPC: G06F1/32 ,  G06F3/06

    CPC classification number: G06F1/3203 ,  G06F1/3225 ,  G06F1/3275 ,  G06F3/0625 ,  Y02D10/14

    Abstract: The present application describes embodiments of a method that includes modifying an operating point of at least one of a memory physical layer interface or a memory controller in response to changes in bandwidth utilization of the memory physical layer interface. The present application also describes embodiments of an apparatus that includes a memory controller, a memory physical layer interface, and a power management controller to modify an operating point of at least one of the memory physical layer interface or the memory controller in response to changes in bandwidth utilization of the memory physical layer interface.

    Abstract translation: 本申请描述了一种方法的实施例，其包括响应于存储器物理层接口的带宽利用率的变化而修改存储器物理层接口或存储器控制器中的至少一个的操作点。 本申请还描述了一种装置的实施例，其包括存储器控制器，存储器物理层接口和功率管理控制器，以响应于存储器物理层接口或存储器控制器中的至少一个的操作点来修改 内存物理层接口的带宽利用率。

    Allocating power to compute units based on energy efficiency
    30.
    发明授权
    Allocating power to compute units based on energy efficiency 有权
    基于能源效率分配功率到计算单位

    公开(公告)号：US09261935B2

    公开(公告)日：2016-02-16

    申请号：US13932697

    申请日：2013-07-01

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Alexander J. Branover ,  Ashish Jain

    IPC: G06F1/20 ,  G06F1/32

    CPC classification number: G06F1/3206 ,  G06F1/206 ,  G06F1/3287 ,  Y02D10/171

    Abstract: A method is provided for allocating power to compute units based on energy efficiency. Some embodiments of the method include allocating portions of a power budget of a system-on-a-chip (SOC) to a plurality of compute units implemented on the SOC based on ratios of a performance level for each compute unit to a power consumed by the compute unit operating at the performance level. An SOC is provided that includes a plurality of compute units and a power management controller to allocate portions of a power budget of the SOC to the plurality of compute units based on ratios of a performance level for each compute unit to a power consumed by the compute unit operating at the performance level.

    Abstract translation: 提供了一种基于能量效率来分配功率到计算单元的方法。 该方法的一些实施例包括将基于片上系统（SOC）的功率预算的部分分配给在SOC上实现的多个计算单元，该多个计算单元基于每个计算单元的性能级别与由 计算单元在性能级别运行。 提供了包括多个计算单元的SOC，以及功率管理控制器，用于基于每个计算单元的性能水平与计算所消耗的功率的比率来将多个计算单元的功率预算的部分分配给多个计算单元 单位在性能水平运行。

Patent Agency Ranking