公开(公告)号：US20140176187A1

公开(公告)日：2014-06-26

申请号：US13726145

申请日：2012-12-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Nuwan S. Jayasena ,  Michael J. Schulte ,  Gabriel H. Loh ,  Michael Ignatowski

IPC: H03K19/177

CPC classification number: H03K19/1776 ,  G06F11/1004 ,  G06F13/1668 ,  G06F13/4234 ,  G06F15/7867 ,  G11C7/1006 ,  G11C7/1048 ,  G11C29/70 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H03K19/17776 ,  Y02D10/14 ,  Y02D10/151

Abstract: A die-stacked memory device incorporates a reconfigurable logic device to provide implementation flexibility in performing various data manipulation operations and other memory operations that use data stored in the die-stacked memory device or that result in data that is to be stored in the die-stacked memory device. One or more configuration files representing corresponding logic configurations for the reconfigurable logic device can be stored in a configuration store at the die-stacked memory device, and a configuration controller can program a reconfigurable logic fabric of the reconfigurable logic device using a selected one of the configuration files. Due to the integration of the logic dies and the memory dies, the reconfigurable logic device can perform various data manipulation operations with higher bandwidth and lower latency and power consumption compared to devices external to the die-stacked memory device.

Abstract translation: 芯片堆叠的存储器件包括可重构逻辑器件，以在执行各种数据操作操作和使用存储在管芯堆叠的存储器件中的数据的其他存储器操作中提供实现灵活性，或者导致要存储在管芯堆叠存储器件中的数据。 堆叠式存储设备。 代表可重配置逻辑器件的相应逻辑配置的一个或多个配置文件可被存储在管芯堆叠的存储器件的配置存储器中，并且配置控制器可使用所选择的一个存储器件对可重新配置的逻辑器件进行编程 配置文件。 由于逻辑管芯和存储器管芯的集成，与可堆叠存储器件外部的器件相比，可重构逻辑器件可以执行具有更高带宽和更低延迟和功耗的各种数据操作操作。

公开(公告)号：US20240419735A1

公开(公告)日：2024-12-19

申请号：US18436116

申请日：2024-02-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Ganesh Dasika ,  Michael Ignatowski ,  Michael J. Schulte ,  Gabriel H. Loh ,  Valentina Salapura ,  Angela Beth Dalton

IPC: G06F16/901 ,  G06F15/80

Abstract: An accelerator device includes a first processing unit to access a structure of a graph dataset, and a second processing unit coupled with the first processing unit to perform computations based on data values in the graph dataset.

公开(公告)号：US09442557B2

公开(公告)日：2016-09-13

申请号：US14075645

申请日：2013-11-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Nuwan S. Jayasena ,  Yasuko Eckert ,  Madhu Saravana Sibi Govindan ,  William L. Bircher ,  Michael J. Schulte ,  Srilatha Manne

IPC: G06F1/32 ,  G06F1/20

CPC classification number: G06F1/3234 ,  G06F1/206

Abstract: The described embodiments include a computing device with one or more entities (processor cores, processors, etc.). In some embodiments, during operation, a thermal power management unit in the computing device uses a linear prediction to compute a predicted duration of a next idle period for an entity based on the duration of one or more previous idle periods for the entity. Based on the predicted duration of the next idle period, the thermal power management unit configures the entity to operate in a corresponding idle state.

Abstract translation: 所描述的实施例包括具有一个或多个实体（处理器核心，处理器等）的计算设备。 在一些实施例中，在操作期间，计算设备中的热功率管理单元使用线性预测来基于实体的一个或多个先前空闲周期的持续时间来计算实体的下一个空闲周期的预测持续时间。 基于下一个空闲周期的预测持续时间，热功率管理单元将实体配置为在相应的空闲状态下工作。

公开(公告)号：US09344091B2

公开(公告)日：2016-05-17

申请号：US14551147

申请日：2014-11-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Nuwan S. Jayasena ,  Michael J. Schulte ,  Gabriel H. Loh ,  Michael Ignatowski

IPC: H03K19/177 ,  G11C7/00 ,  G06F15/78 ,  G06F13/16 ,  G06F11/10 ,  G06F13/42 ,  G11C7/10 ,  G11C29/00

CPC classification number: H03K19/1776 ,  G06F11/1004 ,  G06F13/1668 ,  G06F13/4234 ,  G06F15/7867 ,  G11C7/1006 ,  G11C7/1048 ,  G11C29/70 ,  H01L2224/16227 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H03K19/17776 ,  Y02D10/14 ,  Y02D10/151

Abstract: A die-stacked memory device incorporates a reconfigurable logic device to provide implementation flexibility in performing various data manipulation operations and other memory operations that use data stored in the die-stacked memory device or that result in data that is to be stored in the die-stacked memory device. One or more configuration files representing corresponding logic configurations for the reconfigurable logic device can be stored in a configuration store at the die-stacked memory device, and a configuration controller can program a reconfigurable logic fabric of the reconfigurable logic device using a selected one of the configuration files. Due to the integration of the logic dies and the memory dies, the reconfigurable logic device can perform various data manipulation operations with higher bandwidth and lower latency and power consumption compared to devices external to the die-stacked memory device.

Abstract translation: 芯片堆叠的存储器件包括可重构逻辑器件，以在执行各种数据操作操作和使用存储在管芯堆叠的存储器件中的数据的其他存储器操作中提供实现灵活性，或者导致要存储在管芯堆叠存储器件中的数据。 堆叠式存储设备。 代表可重配置逻辑器件的相应逻辑配置的一个或多个配置文件可被存储在管芯堆叠的存储器件的配置存储器中，并且配置控制器可使用所选择的一个存储器件对可重新配置的逻辑器件进行编程 配置文件。 由于逻辑管芯和存储器管芯的集成，与可堆叠存储器件外部的器件相比，可重构逻辑器件可以执行具有更高带宽和更低延迟和功耗的各种数据操作操作。

公开(公告)号：US09218204B2

公开(公告)日：2015-12-22

申请号：US13725724

申请日：2012-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： James M. O'Connor ,  Michael J. Schulte ,  Nuwan S. Jayasena ,  Gabriel H. Loh

IPC: G06F9/50 ,  G06F9/52

CPC classification number: G06F9/50 ,  G06F9/526 ,  G06F2209/521 ,  G06F2209/522

Abstract: A system includes an atomic processing engine (APE) coupled to an interconnect. The interconnect is to couple to one or more processor cores. The APE receives a plurality of commands from the one or more processor cores through the interconnect. In response to a first command, the APE performs a first plurality of operations associated with the first command. The first plurality of operations references multiple memory locations, at least one of which is shared between two or more threads executed by the one or more processor cores.

Abstract translation: 系统包括耦合到互连的原子处理引擎（APE）。 互连将耦合到一个或多个处理器内核。 APE通过互连从一个或多个处理器核接收多个命令。 响应于第一命令，APE执行与第一命令相关联的第一多个操作。 第一组多个操作引用多个存储器位置，其中至少一个在一个或多个处理器核心执行的两个或多个线程之间共享。

公开(公告)号：US20140181556A1

公开(公告)日：2014-06-26

申请号：US13724599

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Yasuko Eckert ,  Srilatha Manne ,  William L. Bircher ,  Mahdu S.S. Govindan ,  Michael J. Schulte ,  Manish Arora

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172

Abstract: A method and apparatus for exiting a low power state based on a prior prediction is disclosed. An integrated circuit (IC) includes a functional unit configured to, during operation, cycle between intervals of an active state and intervals of an idle state. The IC also include a power management unit configured to place the functional unit in a low power state responsive to the functional unit entering the idle state. The power management unit is further configured to preemptively cause the functional unit to exit the low power state at a predetermined time after entering the low power. The predetermined time is based on a prediction of idle state duration made prior to entering the low power state. The prediction may be generated by a prediction unit, based on a history of durations of intervals in which the functional unit was in the idle state.

Abstract translation: 公开了一种基于先前预测退出低功率状态的方法和装置。 集成电路（IC）包括功能单元，其被配置为在操作期间在活动状态的间隔和空闲状态的间隔之间循环。 IC还包括电源管理单元，其被配置为响应于功能单元进入空闲状态而将功能单元置于低功率状态。 电源管理单元还被配置为在进入低功率之后的预定时间，预先使功能单元退出低功率状态。 预定时间基于在进入低功率状态之前进行的空闲状态持续时间的预测。 预测可以由预测单元基于功能单元处于空闲状态的间隔的持续时间的历史来生成。

公开(公告)号：US20140181554A1

公开(公告)日：2014-06-26

申请号：US13724133

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Srilatha Manne ,  Sanjay Pant ,  Youngtaek Kim ,  Michael J. Schulte

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3243 ,  Y02D10/152

Abstract: A multi-core data processor includes multiple data processor cores and a circuit. The multiple data processor cores each include a power state controller having a first input for receiving an idle signal, a second input for receiving a release signal, a third input for receiving a control signal, and an output for providing a current power state. In response to the idle signal, the power state controller causes a corresponding data processor core to enter an idle state. In response to the release signal, the power state controller changes the current power state from the idle state to an active state in dependence on the control signal. The circuit is coupled to each of the multiple data processor cores for providing the control signal in response to current power states in the multiple data processor cores.

Abstract translation: 多核数据处理器包括多个数据处理器核心和一个电路。 多个数据处理器核心各自包括具有用于接收空闲信号的第一输入的功率状态控制器，用于接收释放信号的第二输入，用于接收控制信号的第三输入和用于提供当前功率状态的输出。 响应于空闲信号，电源状态控制器使相应的数据处理器核进入空闲状态。 响应于释放信号，功率状态控制器根据控制信号将当前功率状态从空闲状态改变到活动状态。 电路耦合到多个数据处理器核心中的每一个，以响应于多个数据处理器核心中的当前功率状态来提供控制信号。

公开(公告)号：US20140181553A1

公开(公告)日：2014-06-26

申请号：US13723868

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Yasuko Eckert ,  Srilatha Manne ,  William L. Bircher ,  Mahdu S.S. Govindan ,  Michael J. Schulte

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/3206 ,  G06F1/3237 ,  G06F1/3243 ,  G06F1/329 ,  Y02D10/128 ,  Y02D10/152 ,  Y02D10/24 ,  Y02D50/20

Abstract: A method and apparatus for idle phase prediction in integrated circuits is disclosed. In one embodiment, an integrated circuit (IC) includes a functional unit configured to cycle between intervals of an active state and an idle state. The IC further includes a prediction unit configured to record a history of idle state durations for a plurality of intervals of the idle state. Based on the history of idle state durations, the prediction unit is configured to generate a prediction of the duration of the next interval of the idle state. The prediction may be used by a power management unit to, among other uses, determine whether to place the functional unit in a low power (e.g., sleep) state.

Abstract translation: 公开了一种用于集成电路中的空闲相位预测的方法和装置。 在一个实施例中，集成电路（IC）包括被配置为在活动状态的间隔和空闲状态之间循环的功能单元。 IC还包括：预测单元，被配置为在空闲状态的多个间隔中记录空闲状态持续时间的历史。 基于空闲状态持续时间的历史，预测单元被配置为生成空闲状态的下一个间隔的持续时间的预测。 电力管理单元可以使用该预测，除了其他用途之外，确定是否将功能单元置于低功率（例如睡眠）状态。

公开(公告)号：US20140181417A1

公开(公告)日：2014-06-26

申请号：US13726146

申请日：2012-12-23

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Gabriel H. Loh ,  Bradford M. Beckmann ,  Lisa R. Hsu ,  Michael Ignatowski ,  Michael J. Schulte

IPC: G06F12/08

CPC classification number: G06F12/0828 ,  G11C5/025 ,  G11C8/12 ,  G11C29/12 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/1461 ,  H01L2924/15311 ,  Y02D10/13 ,  H01L2924/00

Abstract: A die-stacked memory device implements an integrated coherency manager to offload cache coherency protocol operations for the devices of a processing system. The die-stacked memory device includes a set of one or more stacked memory dies and a set of one or more logic dies. The one or more logic dies implement hardware logic providing a memory interface and the coherency manager. The memory interface operates to perform memory accesses in response to memory access requests from the coherency manager and the one or more external devices. The coherency manager comprises logic to perform coherency operations for shared data stored at the stacked memory dies. Due to the integration of the logic dies and the memory dies, the coherency manager can access shared data stored in the memory dies and perform related coherency operations with higher bandwidth and lower latency and power consumption compared to the external devices.

Abstract translation: 堆叠堆叠的存储器件实现集成的一致性管理器以卸载处理系统的设备的高速缓存一致性协议操作。 芯片堆叠的存储器件包括一组一个或多个堆叠的存储器管芯和一组一个或多个逻辑管芯。 一个或多个逻辑模块实现提供存储器接口和一致性管理器的硬件逻辑。 存储器接口操作以响应来自一致性管理器和一个或多个外部设备的存储器访问请求来执行存储器访问。 相关性管理器包括对存储在堆叠存储器管芯上的共享数据执行一致性操作的逻辑。 由于逻辑管芯和存储器管芯的集成，一致性管理器可以访问存储在存储器管芯中的共享数据，并且与外部器件相比具有更高带宽和更低的延迟和功耗的相关一致性操作。

公开(公告)号：US20140149772A1

公开(公告)日：2014-05-29

申请号：US14075645

申请日：2013-11-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Nuwan S. Jayasena ,  Yasuko Eckert ,  Madhu Saravana Sibi Govindan ,  William L. Bircher ,  Michael J. Schulte ,  Srilatha Manne

IPC: G06F1/32

CPC classification number: G06F1/3234 ,  G06F1/206

Abstract: The described embodiments include a computing device with one or more entities (processor cores, processors, etc.). In some embodiments, during operation, a thermal power management unit in the computing device uses a linear prediction to compute a predicted duration of a next idle period for an entity based on the duration of one or more previous idle periods for the entity. Based on the predicted duration of the next idle period, the thermal power management unit configures the entity to operate in a corresponding idle state.

Abstract translation: 所描述的实施例包括具有一个或多个实体（处理器核心，处理器等）的计算设备。 在一些实施例中，在操作期间，计算设备中的热功率管理单元使用线性预测来基于实体的一个或多个先前空闲周期的持续时间来计算实体的下一个空闲周期的预测持续时间。 基于下一个空闲周期的预测持续时间，热功率管理单元将实体配置为在相应的空闲状态下工作。