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    PRAMs having a plurality of active regions located vertically in sequence and methods of forming the same
    21.
    发明申请
    PRAMs having a plurality of active regions located vertically in sequence and methods of forming the same 有权
    具有多个有序区域的垂直位置的PRAM及其形成方法

    公开(公告)号：US20060076548A1

    公开(公告)日：2006-04-13

    申请号：US11246863

    申请日：2005-10-07

    申请人： Jae-Hyun Park ,  Hyeong-Geun An ,  Su-Jin Ahn ,  Yoon-Jong Song ,  Hyung-Joo Youn ,  Kyu-Chul Kim

    发明人： Jae-Hyun Park ,  Hyeong-Geun An ,  Su-Jin Ahn ,  Yoon-Jong Song ,  Hyung-Joo Youn ,  Kyu-Chul Kim

    IPC分类号： H01L29/02

    CPC分类号： H01L27/2436 ,  H01L45/06 ,  H01L45/144

    摘要： There are provided PRAMS having a plurality of active regions located vertically in sequence and methods of forming the same. The PRAM and the method provide an approach to rapidly changing phase in a phase change layer pattern with a given design rule. A semiconductor substrate defining at least one reference active region is prepared in a cell array region and a peripheral circuit region. Other semiconductor substrates on a vertical line passing a main surface of the reference active region are located in sequence. The other semiconductor substrates define other active regions, respectively. A lower cell gate pattern is formed on the semiconductor substrate of the reference active region, and upper cell gate patterns are disposed on the other semiconductor substrates of the other active regions, respectively.

    摘要翻译： 提供了具有顺序定位的多个活性区域和其形成方法的PRAMS。 PRAM和该方法提供了用给定设计规则快速改变相变层图案中的相位的方法。 在单元阵列区域和外围电路区域中制备限定至少一个参考有源区的半导体衬底。 在通过参考有源区域的主表面的垂直线上的其它半导体衬底依次定位。 其他半导体衬底分别限定其它有源区。 在参考有源区的半导体衬底上形成下电池栅极图案，并且上电池栅极图案分别设置在其它有源区的其它半导体衬底上。

    Phase change memory device and method for forming the same
    22.
    发明申请
    Phase change memory device and method for forming the same 有权
    相变存储器件及其形成方法

    公开(公告)号：US20060011902A1

    公开(公告)日：2006-01-19

    申请号：US11149755

    申请日：2005-06-10

    申请人： Yoon-Jong Song ,  Se-Ho Lee ,  Ki-Nam Kim ,  Su-Youn Lee ,  Jae-Hyun Park

    发明人： Yoon-Jong Song ,  Se-Ho Lee ,  Ki-Nam Kim ,  Su-Youn Lee ,  Jae-Hyun Park

    IPC分类号： H01L47/00

    CPC分类号： H01L45/06 ,  G11C2213/52 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/141 ,  H01L45/1683 ,  Y10S438/90

    摘要： A phase change memory device includes a mold layer disposed on a substrate, a heating electrode, a filling insulation pattern and a phase change material pattern. The heating electrode is disposed in an opening exposing the substrate through the mold layer. The heating electrode is formed in a substantially cylindrical shape, having its sidewalls conformally disposed on the lower inner walls of the opening. The filling insulation pattern fills an empty region surrounded by the sidewalls of the heating electrode. The phase change material pattern is disposed on the mold layer and downwardly extended to fill the empty part of the opening. The phase change material pattern contacts the top surfaces of the sidewalls of the heating electrode.

    摘要翻译： 相变存储器件包括设置在基板上的模具层，加热电极，填充绝缘图案和相变材料图案。 加热电极设置在使基板穿过模具层的开口中。 加热电极形成为大致圆筒形，其侧壁共形地设置在开口的下内壁上。 填充绝缘图案填充由加热电极的侧壁围绕的空白区域。 相变材料图案设置在模具层上并向下延伸以填充开口的空的部分。 相变材料图案接触加热电极的侧壁的顶表面。

    Methods for forming electronic devices including capacitor structures
    23.
    发明授权
    Methods for forming electronic devices including capacitor structures 失效
    用于形成包括电容器结构的电子器件的方法

    公开(公告)号：US06911362B2

    公开(公告)日：2005-06-28

    申请号：US10635195

    申请日：2003-08-06

    申请人： Ki-Nam Kim ,  Yoon-Jong Song ,  Heung-Jin Joo

    发明人： Ki-Nam Kim ,  Yoon-Jong Song ,  Heung-Jin Joo

    IPC分类号： H01L27/105 ,  H01L21/8246 ,  H01L27/115 ,  H01L21/8242

    CPC分类号： H01L27/11502 ,  H01L27/11507

    摘要： Methods for forming an electronic device can include forming a capacitor structure on a portion of a substrate with the capacitor structure including a first electrode on the substrate, a capacitor dielectric on the first electrode, a second electrode on the dielectric, and a hard mask on the second electrode. More particularly, the capacitor dielectric can be between the first and second electrodes, the first electrode and the capacitor dielectric can be between the second electrode and the substrate, and the first and second electrodes and the capacitor dielectric can be between the hard mask and the substrate. An interlayer dielectric layer can be formed on the hard mask and on portions of the substrate surrounding the capacitor structure, and portions of the interlayer dielectric layer can be removed to expose the hard mask while maintaining portions of the interlayer dielectric layer on portions of the substrate surrounding the capacitor structure. The hard mask can then be removed thereby exposing portions of the second electrode while maintaining the portions of the interlayer dielectric layer on portions of the substrate surrounding the capacitor.

    摘要翻译： 用于形成电子器件的方法可以包括在衬底的一部分上形成电容器结构，其中电容器结构包括在衬底上的第一电极，第一电极上的电容器电介质，电介质上的第二电极， 第二电极。 更具体地，电容器电介质可以在第一和第二电极之间，第一电极和电容器电介质可以在第二电极和衬底之间，并且第一和第二电极和电容器电介质可以在硬掩模和第二电极之间 基质。 可以在硬掩模和围绕电容器结构的基板的部分上形成层间电介质层，并且可以去除层间介电层的部分以暴露硬掩模，同时将层间电介质层的部分保持在基板的部分上 围绕电容器结构。 然后可以去除硬掩模，从而暴露第二电极的部分，同时保持层间电介质层的部分在包围电容器的基板的部分上。

    MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    24.
    发明申请
    MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    磁性随机访问存储器件及其制造方法

    公开(公告)号：US20170069684A1

    公开(公告)日：2017-03-09

    申请号：US15157403

    申请日：2016-05-17

    申请人： Ki-Seok SUH ,  Jae-Chul SHIM ,  Kil-Ho LEE ,  Yong-Seok CHUNG ,  Gwan-Hyeob KOH ,  Yoon-Jong SONG

    发明人： Ki-Seok SUH ,  Jae-Chul SHIM ,  Kil-Ho LEE ,  Yong-Seok CHUNG ,  Gwan-Hyeob KOH ,  Yoon-Jong SONG

    IPC分类号： H01L27/22 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

    CPC分类号： H01L27/222 ,  H01L43/12

    摘要： A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.

    摘要翻译： 制造MRAM器件的方法包括在衬底上依次形成第一绝缘层和蚀刻停止层。 通过蚀刻停止层和第一绝缘中间层形成下电极。 在下电极和蚀刻停止层上依次形成MTJ结构层和上电极。 通过使用上电极作为蚀刻掩模的物理蚀刻工艺对MTJ结构层进行构图，以形成至少部分地接触下电极的MTJ结构。 第一绝缘中间层由蚀刻停止层保护，因此不被物理蚀刻工艺蚀刻。

    Semiconductor device including uniform contact plugs and a method of manufacturing the same
    25.
    发明授权
    Semiconductor device including uniform contact plugs and a method of manufacturing the same 有权
    包括均匀接触塞的半导体器件及其制造方法

    公开(公告)号：US08203135B2

    公开(公告)日：2012-06-19

    申请号：US12697620

    申请日：2010-02-01

    申请人： Kyu-Rie Sim ,  Jung-Hoon Park ,  Yoon-Jong Song ,  Jae-Min Shin ,  Shin-Hee Han

    发明人： Kyu-Rie Sim ,  Jung-Hoon Park ,  Yoon-Jong Song ,  Jae-Min Shin ,  Shin-Hee Han

    IPC分类号： H01L29/41

    CPC分类号： H01L27/24 ,  H01L27/222

    摘要： A semiconductor device, a semiconductor module, an electronic apparatus and methods of fabricating and manufacturing the same are provided. The semiconductor device includes a lower interconnection formed on a substrate, a plurality of control patterns formed on the lower interconnection, a plurality of lower contact plug patterns formed on the control patterns, a plurality of storage patterns formed on the lower contact plug patterns, a plurality of upper electrodes formed on the storage patterns, and a plurality of upper interconnections formed on the upper electrodes. The lower contact plug patterns each include at least two contact holes having different sizes, a plurality of sidewall patterns formed on inner sidewalls of the two contact holes and wherein the sidewall patterns have different thicknesses from one another. The semiconductor device further includes a plurality of electrode patterns conformably formed on the inside of the sidewall patterns and having size errors less than 10%, and a plurality of filling patterns formed inside the electrode patterns and completely filling the inside of the contact holes.

    摘要翻译： 提供半导体器件，半导体模块，电子设备及其制造和制造方法。 半导体器件包括形成在衬底上的下互连，形成在下互连上的多个控制图案，形成在控制图案上的多个下接触插塞图案，形成在下接触插塞图案上的多个存储图案， 形成在存储图案上的多个上电极和形成在上电极上的多个上互连。 下接触插头图案各自包括具有不同尺寸的至少两个接触孔，多个侧壁图案形成在两个接触孔的内侧壁上，并且其中侧壁图案具有彼此不同的厚度。 半导体器件还包括多个沿着侧壁图案的内侧形成并且具有小于10％的尺寸误差的电极图案，以及形成在电极图案内并且完全填充接触孔内部的多个填充图案。

    Phase change memory devices having dual lower electrodes and methods of fabricating the same
    26.
    发明授权
    Phase change memory devices having dual lower electrodes and methods of fabricating the same 有权
    具有双下电极的相变存储器件及其制造方法

    公开(公告)号：US08129214B2

    公开(公告)日：2012-03-06

    申请号：US12709536

    申请日：2010-02-22

    申请人： Yoon-Jong Song ,  Kyung-Chang Ryoo ,  Dong-Won Lim

    发明人： Yoon-Jong Song ,  Kyung-Chang Ryoo ,  Dong-Won Lim

    IPC分类号： H01L21/00 ,  H01L45/00

    CPC分类号： H01L45/144 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1273 ,  H01L45/1675

    摘要： A semiconductor device includes a semiconductor substrate and a lower interlayer insulating layer disposed on the substrate. An opening passing through the lower interlayer insulating layer and exposing the substrate is included. A buried insulating pattern is disposed in the opening. First and second conductive layer patterns are sequentially stacked to surround the sidewall and bottom of the buried insulating pattern. A phase change material pattern is included, which is disposed on the lower interlayer insulating layer in contact with a top surface of the second conductive layer pattern, and spaced apart from the first conductive layer pattern. An upper interlayer insulating layer covering the lower interlayer insulating layer and the phase change material pattern is included. A conductive plug is included, which passes through the upper interlayer insulating layer and is electrically connected to the phase change material pattern. A method of fabricating the semiconductor device is also provided.

    摘要翻译： 半导体器件包括半导体衬底和设置在衬底上的下层间绝缘层。 包括通过下层间绝缘层并露出衬底的开口。 掩埋绝缘图案设置在开口中。 依次堆叠第一和第二导电层图案以围绕埋入绝缘图案的侧壁和底部。 包括相变材料图案，其设置在与第二导电层图案的顶表面接触并且与第一导电层图案间隔开的下层间绝缘层上。 包括覆盖下层间绝缘层的上层间绝缘层和相变材料图案。 包括导电塞，其穿过上层间绝缘层并电连接到相变材料图案。 还提供了制造半导体器件的方法。

    Phase change memory device and method of fabricating the same
    29.
    发明申请
    Phase change memory device and method of fabricating the same 有权
    相变存储器件及其制造方法

    公开(公告)号：US20090242866A1

    公开(公告)日：2009-10-01

    申请号：US12382781

    申请日：2009-03-24

    申请人： Seung-Pil Ko ,  Jae-Hee Oh ,  Jung-Hoon Park ,  Yoon-Jong Song ,  Jae-Hyun Park ,  Dong-Won Lim

    发明人： Seung-Pil Ko ,  Jae-Hee Oh ,  Jung-Hoon Park ,  Yoon-Jong Song ,  Jae-Hyun Park ,  Dong-Won Lim

    IPC分类号： H01L47/00 ,  H01L21/00

    CPC分类号： H01L45/144 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1683

    摘要： A semiconductor device includes an insulating layer on a substrate, a first electrode in the insulating layer having a first upper surface and a second upper surface, a second electrode in the insulating layer spaced apart from the first electrode by a first distance and having a third upper surface and a fourth upper surface, the third upper surface being disposed at a substantially same level as the first upper surface, and the fourth upper surface being disposed at a substantially same level as the second upper surface, a first phase change material pattern covering a part of the first upper surface of the first electrode, and a second phase change material pattern covering a part of the third upper surface of the second electrode, wherein an interface region between the second phase change pattern and the second electrode is spaced apart from an interface region between the first phase change pattern and the first electrode by a second distance greater than the first distance.

    摘要翻译： 半导体器件在衬底上包括绝缘层，绝缘层中的第一电极具有第一上表面和第二上表面，绝缘层中的第二电极与第一电极隔开第一距离，并具有第三距离 上表面和第四上表面，所述第三上表面设置在与所述第一上表面基本相同的高度，所述第四上表面设置在与所述第二上表面基本相同的水平面上，所述第一相变材料图案覆盖 第一电极的第一上表面的一部分和覆盖第二电极的第三上表面的一部分的第二相变材料图案，其中第二相变图案和第二电极之间的界面区域与 所述第一相变图案和所述第一电极之间的界面区域大于所述第一距离的第二距离。

    Phase change memory and method of fabricating the same
    30.
    发明申请
    Phase change memory and method of fabricating the same 失效
    相变记忆及其制造方法

    公开(公告)号：US20090163023A1

    公开(公告)日：2009-06-25

    申请号：US12314884

    申请日：2008-12-18

    申请人： Yoon-Jong Song ,  Byung-Seo Kim ,  Kyung-Chang Ryoo

    发明人： Yoon-Jong Song ,  Byung-Seo Kim ,  Kyung-Chang Ryoo

    IPC分类号： H01L21/44

    CPC分类号： H01L45/1675 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144

    摘要： A method of fabricating a phase change memory includes forming a lower electrode on a semiconductor substrate, forming a phase change pattern, an upper electrode, and a hard mask pattern sequentially on the lower electrode, a width of a bottom surface of the hard mask pattern being greater than a width of a top surface of the hard mask pattern, the bottom surface of the hard mask pattern facing the upper electrode and being opposite the top surface of the hard mask pattern, and forming a capping layer to cover the top surface of the hard mask pattern and sidewalls of the hard mask pattern, phase change pattern, and upper electrode.

    摘要翻译： 制造相变存储器的方法包括在半导体衬底上形成下电极，在下电极上依次形成相变图案，上电极和硬掩模图案，硬掩模图案的底面宽度 大于硬掩模图案的顶表面的宽度，硬掩模图案的底表面面向上电极并且与硬掩模图案的顶表面相对，并且形成覆盖层以覆盖硬掩模图案的顶表面 硬掩模图案和硬掩模图案的侧壁，相变图案和上电极。