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    High ruggedness heterojunction bipolar transistor structure
    25.
    发明授权
    High ruggedness heterojunction bipolar transistor structure 有权

    公开(公告)号：US11049936B2

    公开(公告)日：2021-06-29

    申请号：US16292365

    申请日：2019-03-05

    Applicant: VISUAL PHOTONICS EPITAXY CO., LTD.

    Inventor： Yu-Chung Chin ,  Chao-Hsing Huang ,  Min-Nan Tseng ,  Kai-Yu Chen

    IPC: H01L33/00 ,  H01L21/00 ,  H01L29/08 ,  H01L29/205 ,  H01L29/737 ,  H01L27/082 ,  H01L29/732

    Abstract: The disclosure provides a high ruggedness HBT structure, including: a sub-collector layer on a substrate and formed of an N-type III-V semiconductor material; a collector layer on the sub-collector layer and formed of a III-V semiconductor material; a base layer on the collector layer and formed of a P-type III-V semiconductor material; an emitter layer on the base layer and formed of one of N-type semiconductor materials of InGaP, InGaAsP and InAlGaP; a first emitter cap layer on the emitter layer and formed of one of undoped or N-type semiconductor materials of AlxGa1-xAs, AlxGa1-xAs1-yNy, AlxGa1-xAs1-zPz, AlxGa1-xAs1-wSbw, and InrAlxGa1-x-rAs, x having a highest value between 0.05≤x≤0.4, and y, z, r, w≤0.1; a second emitter cap layer on the first emitter cap layer and formed of an N-type III-V semiconductor material; and an ohmic contact layer on the second emitter cap layer and formed of an N-type III-V semiconductor material.

    VERTICAL CAVITY SURFACE EMITTING LASER DIODE (VCSEL) HAVING ALGAASP LAYER WITH COMPRESSIVE STRAIN
    26.
    发明申请
    VERTICAL CAVITY SURFACE EMITTING LASER DIODE (VCSEL) HAVING ALGAASP LAYER WITH COMPRESSIVE STRAIN 有权

    公开(公告)号：US20210021104A1

    公开(公告)日：2021-01-21

    申请号：US16931541

    申请日：2020-07-17

    Applicant: VISUAL PHOTONICS EPITAXY CO., LTD.

    Inventor： Chao-Hsing Huang ,  Yu-Chung Chin ,  Van-Truong Dai

    IPC: H01S5/34 ,  H01S5/183

    Abstract: Provided is a vertical cavity surface emitting laser diode (VCSEL) with low compressive strain DBR layer, including a GaAs substrate, a lower DBR layer, a lower spacer layer, an active region, an upper spacer layer and an upper DBR layer. The lower or the upper DBR layer includes multiple low refractive index layers and multiple high refractive index layers. The lower DBR layer, the lower spacer layer, the upper spacer layer or the upper DBR layer contains AlxGa1-xAs1-yPy, where the lattice constant of AlxGa1-xAs1-yPy is greater than that of the GaAs substrate. This can moderately reduce excessive compressive strain due to lattice mismatch or avoid tensile strain during the epitaxial growth, thereby reducing the chance of deformation and bowing of the VCSEL epitaxial wafer or cracking during manufacturing. Additionally, the VCSEL epitaxial layer can be prevented from generating excessive compressive strain or tensile strain during the epitaxial growth.

    HETEROJUNCTION BIPOLAR TRANSISTOR WITH BLOCKING LAYER STRUCTURE
    28.
    发明申请
    HETEROJUNCTION BIPOLAR TRANSISTOR WITH BLOCKING LAYER STRUCTURE 审中-公开
    具有阻塞层结构的异相双极晶体管

    公开(公告)号：US20160049502A1

    公开(公告)日：2016-02-18

    申请号：US14712968

    申请日：2015-05-15

    Applicant: VISUAL PHOTONICS EPITAXY CO., LTD.

    Inventor： Yu-Chung Chin ,  Chao-Hsing Huang ,  Hung-Chi Hsiao

    IPC: H01L29/737 ,  H01L29/207 ,  H01L27/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/778 ,  H01L29/205 ,  H01L29/15

    CPC classification number: H01L29/7371 ,  H01L27/0605 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/155 ,  H01L29/205 ,  H01L29/207 ,  H01L29/66318

    Abstract: Provided is a heterojunction bipolar transistor (HBT), including a GaAs substrate; a subcollector layer stacked on the GaAs substrate, wherein a part of or all of the subcollector layer is formed by N-type group III-V semiconductors doped by at least Te and/or Se; a blocking layer structure directly or indirectly stacked on the subcollector layer, and formed by N-type group III-V semiconductors doped by at least group IV elements, a collector layer stacked on the blocking layer structure, and formed by N-type group III-V semiconductors; a base layer stacked on the collector layer, and formed by P-type group III-V semiconductors; an emitter layer stacked on the base layer and formed by N-type group III-V semiconductors; an emitter cap layer stacked on the emitter layer and formed by N-type group III-V semiconductors; and an ohmic contact layer stacked on the emitter cap layer and formed by N-type group III-V semiconductors.

    Abstract translation: 提供了包括GaAs衬底的异质结双极晶体管（HBT）; 层叠在所述GaAs衬底上的子集电极层，其中所述子集电极层的一部分或全部由通过至少Te和/或Se掺杂的N型III-V族半导体形成; 直接或间接堆叠在子集电极层上的阻挡层结构，由至少IV族元素掺杂的N型III-V族半导体形成，堆叠在阻挡层结构上的集电极层，并由N型III族 -V半导体; 堆叠在集电极层上的基极层，由P型III-V族半导体形成; 由N型III-V族半导体层叠在基极层上的发射极层; 发射极帽层，堆叠在发射极层上，由N型III-V族半导体形成; 以及堆叠在发射极帽层上并由N型III-V族半导体形成的欧姆接触层。

    High electron mobility bipolar transistor
    29.
    发明授权
    High electron mobility bipolar transistor 有权
    高电子迁移双极晶体管

    公开(公告)号：US09130027B2

    公开(公告)日：2015-09-08

    申请号：US14326673

    申请日：2014-07-09

    Applicant: VISUAL PHOTONICS EPITAXY CO., LTD.

    Inventor： Yu-Chung Chin ,  Chao-Hsing Huang

    IPC: H01L21/02 ,  H01L29/06 ,  H01L29/20 ,  H01L29/66 ,  H01L29/778 ,  H01L29/737 ,  H01L29/08 ,  H01L29/205

    CPC classification number: H01L29/778 ,  H01L29/0821 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7371 ,  H01L29/7378 ,  H01L29/7785

    Abstract: A high electron mobility bipolar transistor including a substrate, a pseudomorphic high electron mobility transistor (pHEMT) sub structure, a sub collector/separating layer and a heterojunction bipolar transistor (HBT) sub structure sequentially stacked from bottom to top is disclosed. The sub collector/separating layer and the pHEMT sub structure are combined to form a pHEMT, and the sub collector/separating layer and the HBT sub structure are combined to form an HBT. The carbon concentration in the sub collector/separating layer is within 5×1017 cm−3 and 1×1020 cm−3, and/or the oxygen concentration within 5×1018 cm−3 and 1×1020 cm−3.The lattice during the process of epitaxy growth is stabilized and it is possible to prevent the dopants, the elements, the vacancies or the defects from diffusing into the neighboring layers, thereby improving the problem of mobility degradation and resistance increase, and sustaining the stability of the manufacturing process.

    Abstract translation: 公开了一种高电子迁移率双极晶体管，其包括从底部到顶部顺序层叠的基板，伪晶体高电子迁移率晶体管（pHEMT）子结构，子集电极/分离层和异质结双极晶体管（HBT）子结构。 将亚集电极/分离层和pHEMT子结构组合形成pHEMT，并将亚集电极/分离层和HBT子结构组合形成HBT。 子集电极/分离层中的碳浓度在5×1017cm-3和1×1020cm-3之间，和/或氧浓度在5×1018cm-3和1×1020cm-3之间。 在外延生长过程中的晶格是稳定的，并且可以防止掺杂剂，元素，空位或缺陷扩散到相邻层中，从而改善迁移率降低和电阻增加的问题，并且保持稳定性 制造过程。

    HIGH ELECTRON MOBILITY BIPOLAR TRANSISTOR
    30.
    发明申请
    HIGH ELECTRON MOBILITY BIPOLAR TRANSISTOR 有权
    高电子移动双极晶体管

    公开(公告)号：US20140054647A1

    公开(公告)日：2014-02-27

    申请号：US13910241

    申请日：2013-06-05

    Applicant: Visual Photonics Epitaxy Co., Ltd.

    Inventor： Yu-Chung Chin ,  Chao-Hsing Huang

    IPC: H01L29/737

    CPC classification number: H01L29/778 ,  H01L29/0821 ,  H01L29/20 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7371 ,  H01L29/7378 ,  H01L29/7785

    Abstract: A high electron mobility bipolar transistor including a substrate, a pseudomorphic high electron mobility transistor (pHEMT) sub structure, a sub collector/separating layer and a heterojunction bipolar transistor (HBT) sub structure sequentially stacked from bottom to top is disclosed. The sub collector/separating layer and the pHEMT sub structure are combined to form a pHEMT, and the sub collector/separating layer and the HBT sub structure are combined to form an HBT. The carbon concentration in the sub collector/separating layer is within 5×1017 cm−3 and 1×1020 cm−3, and/or the oxygen concentration within 5×1018 cm−3 and 1×1020 cm−3. The lattice during the process of epitaxy growth is stabilized and it is possible to prevent the dopants, the elements, the vacancies or the defects from diffusing into the neighboring layers, thereby improving the problem of mobility degradation and resistance increase, and sustaining the stability of the manufacturing process.

    Abstract translation: 公开了一种高电子迁移率双极晶体管，其包括从底部到顶部顺序层叠的基板，伪晶体高电子迁移率晶体管（pHEMT）子结构，子集电极/分离层和异质结双极晶体管（HBT）子结构。 将亚集电极/分离层和pHEMT子结构组合形成pHEMT，并将亚集电极/分离层和HBT子结构组合形成HBT。 子集电极/分离层中的碳浓度在5×1017cm-3和1×1020cm-3之间，和/或氧浓度在5×1018cm-3和1×1020cm-3之间。 在外延生长过程中的晶格是稳定的，并且可以防止掺杂剂，元素，空位或缺陷扩散到相邻层中，从而改善迁移率降低和电阻增加的问题，并且保持稳定性 制造过程。

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