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公开(公告)号：US4974098A
公开(公告)日：1990-11-27
申请号：US236961
申请日：1988-08-26
申请人： Tadashi Miyakawa , Masahiro Inoda , Kunio Iba
发明人： Tadashi Miyakawa , Masahiro Inoda , Kunio Iba
IPC分类号： H04N1/407
CPC分类号： H04N1/4076
摘要： According to this invention, since black regions are provided along the advancing direction on an original plate, the dark-time output levels of the linear sensor would not be affected by dust adhered on the original plate or the presence of trimming lines. Since a calibration region is provided, the circuit system can be calibrated with the maximum and minimum values of the signals from the linear sensor to thereby achieve more precise reading of images.
摘要翻译： 根据本发明，由于在原版上沿着前进方向设置黑色区域，因此线性传感器的黑暗时间输出水平将不受附着在原版上的灰尘或修剪线的存在的影响。 由于提供了校准区域，所以可以利用来自线性传感器的信号的最大值和最小值校准电路系统，从而实现图像的更精确的读取。
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22.发明授权Liquid crystal shutter array having microlenses corresponding to the pixel electrodes 失效具有对应于像素电极的微透镜的液晶快门阵列
公开(公告)号：US4836652A
公开(公告)日：1989-06-06
申请号：US120450
申请日：1987-11-13
申请人： Hisao Oishi , Kazuhiko Yanagihara , Tadashi Miyakawa , Takeshi Nakamura , Kazuhiko Akimoto , Mitsuaki Shioji
发明人： Hisao Oishi , Kazuhiko Yanagihara , Tadashi Miyakawa , Takeshi Nakamura , Kazuhiko Akimoto , Mitsuaki Shioji
IPC分类号： B41J2/465 , G02F1/1335 , G02F1/13357
CPC分类号： B41J2/465 , G02F1/133526
摘要： A liquid crystal shutter array requiring no separate focusing lens system. Microlenses for focusing the light incident upon a matrix of pixel electrodes are formed in a transparent substrate of the shutter assembly. A refractive index of light of each of the microlenses is set in a manner such that the incident angle .theta. of the light incident on the liquid crystal of the shutter through the microlenses satisfies; ##EQU1## where P, a, and d respectively represent the size of each of the photomasks, the length of a portion wherein each of the photomasks and corresponding ones of the pixel electrodes overlap, and the thickness of the transparent substrate on the light output side.
摘要翻译： 不需要单独的聚焦透镜系统的液晶快门阵列。 用于将入射到像素电极矩阵上的光聚焦的微透镜形成在快门组件的透明基板中。 每个微透镜的光的折射率被设定为使得通过微透镜入射到快门的液晶上的光的入射角θ满足; 其中P，a和d分别表示每个光掩模的尺寸，其中每个光掩模和对应的像素电极重叠的部分的长度以及光输出上的透明基板的厚度 侧。
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公开(公告)号：US4665303A
公开(公告)日：1987-05-12
申请号：US796123
申请日：1985-11-08
申请人： Tadashi Miyakawa , Yoshiyuki Monma , Yuji Rikiishi , Hideo Seto
发明人： Tadashi Miyakawa , Yoshiyuki Monma , Yuji Rikiishi , Hideo Seto
CPC分类号： G03D13/002
摘要： A thermal developing apparatus develops thermally a photosensitive material having an electrically conductive, heat-generating layer. The apparatus is provided with a heat-insulating cover which is disposed in contact with or close to the surface of the photosensitive material when supplied with electric current, whereby the generation of convection of air at the upper side of the photosenstive material is prevented, and the occurrence of uneven development is eliminated. When the heat-insulating cover is disposed at a distance away from the surface of the photosensitive material, if this distance is less than a predetermined value, no convection of air takes place and, hence, there is no risk of uneven development occurring.
摘要翻译： 热显影装置对具有导电的发热层的感光材料进行热显影。 该设备设置有绝热盖，该绝热盖在被供应电流时与感光材料的表面接触或接近，从而防止在光敏材料的上侧产生空气的对流，并且 消除了不平衡发展的发生。 当绝热盖设置在离感光材料表面一定距离处，如果该距离小于预定值，则不会发生空气对流，因此不会发生不均匀的显影。
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公开(公告)号：US09299409B2
公开(公告)日：2016-03-29
申请号：US14201642
申请日：2014-03-07
CPC分类号： H01L27/228 , G11C7/12 , G11C11/161 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675 , G11C13/0002 , H01L43/08
摘要： According to one embodiment, a semiconductor storage device includes a cell array including resistance change elements formed above a semiconductor substrate; first cell transistors formed on the semiconductor substrate and provided in association with the resistance change elements; first gate electrodes included in the first cell transistor and extending in a first direction; a first bit lines electrically connected to the resistance change elements respectively and extending in a second direction perpendicular to the first direction; a second bit lines electrically connected to one end of a current path of the first cell transistors respectively and extending in the second direction; and first active areas in which the first cell transistors are formed, and which extend in a direction crossing the first direction at a first angle.
摘要翻译： 根据一个实施例，半导体存储装置包括：单元阵列，其包括形成在半导体衬底上方的电阻变化元件; 形成在半导体衬底上并与电阻变化元件相关联地设置的第一单元晶体管; 包括在第一单元晶体管中并沿第一方向延伸的第一栅电极; 分别电连接到所述电阻变化元件并沿垂直于所述第一方向的第二方向延伸的第一位线; 第二位线分别电连接到第一单元晶体管的电流路径的一端并沿第二方向延伸; 以及第一有源区，其中形成有第一单元晶体管，并且在与第一方向交叉的方向上以第一角度延伸。
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公开(公告)号：US20150070982A1
公开(公告)日：2015-03-12
申请号：US14201642
申请日：2014-03-07
IPC分类号： G11C11/16
CPC分类号： H01L27/228 , G11C7/12 , G11C11/161 , G11C11/1653 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1675 , G11C13/0002 , H01L43/08
摘要： According to one embodiment, a semiconductor storage device includes a cell array including resistance change elements formed above a semiconductor substrate; first cell transistors formed on the semiconductor substrate and provided in association with the resistance change elements; first gate electrodes included in the first cell transistor and extending in a first direction; a first bit lines electrically connected to the resistance change elements respectively and extending in a second direction perpendicular to the first direction; a second bit lines electrically connected to one end of a current path of the first cell transistors respectively and extending in the second direction; and first active areas in which the first cell transistors are formed, and which extend in a direction crossing the first direction at a first angle.
摘要翻译： 根据一个实施例，半导体存储装置包括：单元阵列，其包括形成在半导体衬底上方的电阻变化元件; 形成在半导体衬底上并与电阻变化元件相关联地设置的第一单元晶体管; 包括在第一单元晶体管中并沿第一方向延伸的第一栅电极; 分别电连接到所述电阻变化元件并沿垂直于所述第一方向的第二方向延伸的第一位线; 第二位线分别电连接到第一单元晶体管的电流路径的一端并沿第二方向延伸; 以及第一有源区，其中形成有第一单元晶体管，并且在与第一方向交叉的方向上以第一角度延伸。
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公开(公告)号：US20100002493A1
公开(公告)日：2010-01-07
申请号：US12497623
申请日：2009-07-03
CPC分类号： G11C7/12 , G11C11/22 , G11C29/12015 , G11C29/24 , G11C2029/1204
摘要： A precharge circuit precharges a bit line paired with the bit line to which the selected one of the memory cells is connected, by applying to the former bit line an external reference voltage for comparison with a voltage in the bit line caused by selection of the memory cell. A precharge assist circuit, which is connected to the former bit line in parallel with the precharge circuit, charges the bit line to a predetermined potential by using a power supply voltage. A sense amplifier, which is connected to the pair of bit lines, senses and amplifies a potential of a bit line that is connected to a memory cell selected by word lines.
摘要翻译： 预充电电路通过向前一位线施加外部参考电压来与存储器单元所连接的位线配对的位线进行预充电，以便与存储器选择引起的位线中的电压进行比较 细胞。 与预充电电路并联连接到前一位线的预充电辅助电路通过使用电源电压将位线充电至预定电位。 连接到一对位线的感测放大器感测并放大连接到由字线选择的存储单元的位线的电位。
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公开(公告)号：US07486578B2
公开(公告)日：2009-02-03
申请号：US11822244
申请日：2007-07-03
IPC分类号： G11C29/00
摘要： A ferroelectric memory includes a cell block that includes: a block select transistor arranged between a bit line and a local bit line; memory cells arranged between the local bit line and a plate line, each of the memory cells contains a cell transistor and a ferroelectric capacitor connected in series; and a reset transistor arranged between the local bit line and the plate line. A test method for the ferroelectric memory includes: applying a potential that allows the cell transistors to be ON to the word lines; applying a potential that allows the reset transistor to be OFF to the reset line; applying a potential that allows the block select transistor to be ON to the block select line; and applying a stress voltage between the bit line and the plate line.
摘要翻译： 铁电存储器包括：单元块，其包括：布置在位线和局部位线之间的块选择晶体管; 存储单元布置在局部位线和板线之间，每个存储单元包含串联连接的单元晶体管和铁电电容器; 以及布置在局部位线和板线之间的复位晶体管。 铁电存储器的测试方法包括：施加允许单元晶体管接通到字线的电位; 施加允许复位晶体管关闭到复位线的电位; 施加允许块选择晶体管导通到块选择线的电位; 并且在位线和板线之间施加应力电压。
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公开(公告)号：US20080013361A1
公开(公告)日：2008-01-17
申请号：US11822244
申请日：2007-07-03
摘要： A ferroelectric memory includes a cell block that includes: a block select transistor arranged between a bit line and a local bit line; memory cells arranged between the local bit line and a plate line, each of the memory cells contains a cell transistor and a ferroelectric capacitor connected in series; and a reset transistor arranged between the local bit line and the plate line. A test method for the ferroelectric memory includes: applying a potential that allows the cell transistors to be ON to the word lines; applying a potential that allows the reset transistor to be OFF to the reset line; applying a potential that allows the block select transistor to be ON to the block select line; and applying a stress voltage between the bit line and the plate line.
摘要翻译： 铁电存储器包括：单元块，其包括：布置在位线和局部位线之间的块选择晶体管; 存储单元布置在局部位线和板线之间，每个存储单元包含串联连接的单元晶体管和铁电电容器; 以及布置在局部位线和板线之间的复位晶体管。 铁电存储器的测试方法包括：施加允许单元晶体管接通到字线的电位; 施加允许复位晶体管关闭到复位线的电位; 施加允许块选择晶体管导通到块选择线的电位; 并且在位线和板线之间施加应力电压。
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29.发明授权Integrated circuit device provided with series-connected TC parallel unit ferroelectric memory and method for testing the same 有权具有串联连接的TC并联单元铁电存储器的集成电路器件及其测试方法公开(公告)号：US07218546B2
公开(公告)日：2007-05-15
申请号：US11109769
申请日：2005-04-20
CPC分类号： G11C29/50 , G11C8/08 , G11C11/22 , G11C2029/1202
摘要： An integrated circuit device comprises a memory cell block, a word line selecting circuit and a driving circuit. The memory cell block comprises memory cells connected in series. The memory cell comprises a cell transistor including a gate which is connected to a word line, and a ferroelectric capacitor connected to terminals of the cell transistor. The word line selecting circuit successively selects the word lines connected to the cell transistors in the memory cells in the memory cell block in response to address signals successively input from an outside of the device, during an active cycle. The driving circuit applies a given voltage between ends of a current path provided of the cell transistors in the memory cells in the memory cell block, during a time period for which the word lines connected to the cell transistors are successively selected by the word line selecting circuit.
摘要翻译： 集成电路装置包括存储单元块，字线选择电路和驱动电路。 存储单元块包括串联连接的存储器单元。 存储单元包括单元晶体管，其包括连接到字线的栅极和连接到单元晶体管的端子的铁电电容器。 在活动周期期间，字线选择电路响应于从设备的外部连续输入的地址信号，连续地选择连接到存储单元块中的单元晶体管的字线。 在通过字线选择连续选择连接到单元晶体管的字线的时间段期间，驱动电路在存储单元块的存储单元中由单元晶体管提供的电流路径的两端之间施加给定电压 电路。
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公开(公告)号：US20060138503A1
公开(公告)日：2006-06-29
申请号：US11084150
申请日：2005-03-21
IPC分类号： H01L29/94
CPC分类号： H01L27/11502 , H01L27/0207 , H01L27/11507
摘要： A ferroelectric memory comprises a first transistor connected between N1 and N2 nodes, a second transistor connected between the N2 node and an N3 node, a first transistor connected between P1 and P2 nodes, a second transistor connected between the P2 node and a P3 node, a first wiring formed in a first wiring layer to interconnect the N1 node and the P1 node, a second wiring formed in the first wiring layer to interconnect the N3 node and the P3 node, a third wiring formed in a second wiring layer different from the first wiring layer to interconnect the N2 node and the P2 node, a first capacitor whose first electrode is connected to the first wiring, and a second capacitor whose first electrode is connected to the second wiring. Second electrodes of the first and second capacitors are both connected to the N2 node or the P2 node.
摘要翻译： 铁电存储器包括连接在N 1和N 2个节点之间的第一晶体管，连接在N 2节点和N 3节点之间的第二晶体管，连接在P 1和P 2节点之间的第一晶体管，连接在P 2节点和P 3节点，形成在第一布线层中以互连N 1节点和P 1节点的第一布线;形成在第一布线层中以互连N 3节点和P 3节点的第二布线， 形成在与所述第一布线层不同以将所述N 2节点和所述P 2节点互连的第二布线层的第三布线，其第一电极连接到所述第一布线的第一电容器，以及第一电极，其第一电极连接到 第二线。 第一和第二电容器的第二电极都连接到N 2节点或P 2节点。
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