公开(公告)号：US07852165B2

公开(公告)日：2010-12-14

申请号：US12114705

申请日：2008-05-02

Applicant: Ja Yol Lee ,  Sang Heung Lee ,  Hae Cheon Kim ,  Hyun Kyu Yu

Inventor： Ja Yol Lee ,  Sang Heung Lee ,  Hae Cheon Kim ,  Hyun Kyu Yu

IPC: H03B5/12

CPC classification number: H03B5/1231 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1221 ,  H03B5/1253

Abstract: A capacitive-degeneration double cross-coupled voltage-controlled oscillator is provided. The capacitive-degeneration double cross-coupled voltage-controlled oscillator includes a main cross-coupled oscillating unit including an oscillation transistor pair cross-coupled to first and second output nodes of a resonating unit to perform an oscillation operation; and an auxiliary cross-coupled oscillating unit including a positive-feedback transistor pair cross-coupled to the first and second output nodes and the transistor pair of the main cross-coupled oscillating unit and a degeneration capacitance connected between emitters of the positive-feedback transistor pair so as to increase a negative resistance of the main cross-coupled oscillating unit. Accordingly, it is possible to increase a maximum attainable oscillation frequency and to decrease an input capacitance.

Abstract translation: 提供电容变性双交叉耦合压控振荡器。 电容变性双交叉电压控制振荡器包括主交叉耦合振荡单元，其包括交叉耦合到谐振单元的第一和第二输出节点的振荡晶体管对，以执行振荡操作; 以及辅助交叉耦合振荡单元，其包括交叉耦合到第一和第二输出节点的正反馈晶体管对和主交叉耦合振荡单元的晶体管对，以及连接在正反馈晶体管的发射极之间的退化电容 以增加主交叉振荡单元的负电阻。 因此，可以增加最大可获得的振荡频率并降低输入电容。

公开(公告)号：US07666749B2

公开(公告)日：2010-02-23

申请号：US11947098

申请日：2007-11-29

Applicant: Sang Hun Kim ,  Hyun Cheol Bae ,  Sang Heung Lee

Inventor： Sang Hun Kim ,  Hyun Cheol Bae ,  Sang Heung Lee

IPC: H01L21/331 ,  H01L21/8222

CPC classification number: H01L29/7378 ,  H01L29/0821 ,  H01L29/66242

Abstract: Provided are a SiGe semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a buried collector by doping impurity ions into a buried collector region formed on a substrate; forming a collector layer which is an active region and a collector electrode region by forming a Si epitaxial layer on the substrate having the buried collector; forming an isolation layer on the substrate and exposing the collector layer and the collector electrode region; forming a collector pad oxide layer on the collector electrode region; stacking a base epitaxial layer and a pad oxide layer on the substrate having the collector pad oxide layer and patterning the pad oxide layer; forming a first polycrystalline Si (poly-Si) layer on the patterned pad oxide layer; exposing at least a portion of the patterned pad oxide layer by etching the first poly-Si layer; depositing a metal layer on the first poly-Si layer to form a first silicide layer; forming an oxide layer on the substrate having the first silicide layer, and exposing a base-emitter junction and the collector electrode region; forming an emitter electrode and a collector electrode by depositing a second poly-Si layer on the exposed base-emitter junction and collector electrode region; and depositing a metal layer on the emitter and collector electrodes to form a second silicide layer, and forming a base terminal, an emitter terminal, and a collector terminal. In this method, base parasitic resistance can be reduced, an electrical short due to agglomeration caused by Ge can be prevented during the formation of the silicide layer, and the base-emitter junction can be protected using the pad oxide layer from external processes, thereby enhancing process stability and reliability.

Abstract translation: 提供了一种SiGe半导体器件及其制造方法。 该方法包括以下步骤：通过将杂质离子掺杂到形成在衬底上的掩埋集电区中来形成掩埋集电极; 通过在具有该埋设集电体的基板上形成Si外延层，形成作为有源区和集电极区的集电极层; 在所述基板上形成隔离层并使所述集电极层和所述集电极区域露出; 在集电极区域上形成集电极氧化层; 在具有集电极衬垫氧化物层的衬底上堆叠基极外延层和焊盘氧化物层，并对衬垫氧化物层进行构图; 在所述图案化衬垫氧化物层上形成第一多晶Si（多晶硅）层; 通过蚀刻第一多晶硅层来暴露图案化的衬垫氧化物层的至少一部分; 在所述第一多晶硅层上沉积金属层以形成第一硅化物层; 在具有第一硅化物层的衬底上形成氧化物层，并暴露出基极 - 发射极结和集电极区域; 通过在暴露的基极 - 发射极结和集电极区域上沉积第二多晶硅层来形成发射极和集电极; 以及在所述发射极和集电极上沉积金属层以形成第二硅化物层，以及形成基极端子，发射极端子和集电极端子。 在该方法中，可以降低基极寄生电阻，在硅化物层的形成期间可以防止由Ge引起的聚集引起的电短路，并且可以使用衬垫氧化物层从外部工艺来保护基极 - 发射极结，从而 提高工艺稳定性和可靠性。

公开(公告)号：US07511581B2

公开(公告)日：2009-03-31

申请号：US11634004

申请日：2006-12-05

Applicant: Ja Yol Lee ,  Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim ,  Sang Heung Lee

Inventor： Ja Yol Lee ,  Kwi Dong Kim ,  Chong Ki Kwon ,  Jong Dae Kim ,  Sang Heung Lee

IPC: H03L7/00

CPC classification number: H03K23/667 ,  H03L7/0898 ,  H03L7/093 ,  H03L7/099 ,  H03L7/193

Abstract: A wide-band multimode frequency synthesizer using a Phase Locked Loop (PLL) is provided. The multiband frequency synthesizer includes a multimode prescaler, a phase detector/a charge pump, a swallow type frequency divider, and a switching bank LC tuning voltage-controlled oscillator having wide-band and low phase noise characteristics. The multimode prescaler operates in five modes and divides a signal up to 12 GHz. The wide-band frequency synthesizer can be used in various fields such as WLAN/HYPERLAN/DSRC/UWB systems that operate in the frequency range from 2 GHz to 9 GHz. The wide-band multimode frequency synthesizer includes a frequency/phase detector for comparing a frequency and phase of a reference high-frequency signal with a frequency and phase of a feedback high-frequency signal; a charge pump for producing an output current corresponding to the result of the comparison performed by the frequency/phase detector; a loop filter for producing an output voltage corresponding to an accumulated value of the output current of the charge pump; a voltage-controlled oscillator for generating an oscillation signal having a frequency corresponding to the output voltage of the loop filter; and a variable frequency divider for dividing an output signal of the voltage-controlled oscillator by a designated integer value, and outputting the result as a feedback signal, wherein at lease two of an amount of unit pumping charges of the charge pump, an RLC value of the loop filter, an RLC value of the voltage-controlled oscillator, and a divisor value of the variable frequency divider are controlled according to a band.

Abstract translation: 提供了使用锁相环（PLL）的宽带多模频率合成器。 多频率频率合成器包括多模预分频器，相位检测器/电荷泵，燕子式分频器和具有宽带和低相位噪声特性的开关组LC调谐压控振荡器。 多模预分频器以五种模式工作，并将信号分为12 GHz。 宽带频率合成器可用于各种领域，例如在2 GHz至9 GHz频率范围内工作的WLAN / HYPERLAN / DSRC / UWB系统。 宽带多模频率合成器包括用于将参考高频信号的频率和相位与反馈高频信号的频率和相位进行比较的频率/相位检测器; 用于产生与由频率/相位检测器执行的比较结果相对应的输出电流的电荷泵; 环路滤波器，用于产生与电荷泵的输出电流的累积值相对应的输出电压; 用于产生具有与环路滤波器的输出电压对应的频率的振荡信号的压控振荡器; 以及可变分频器，用于将压控振荡器的输出信号除以指定的整数值，并输出该结果作为反馈信号，其中至少两个电荷泵的单位泵送电荷，RLC值 根据频带控制环路滤波器的电压控制振荡器的RLC值和可变分频器的除数值。

公开(公告)号：US20080128754A1

公开(公告)日：2008-06-05

申请号：US11947098

申请日：2007-11-29

Applicant: Sang Hun KIM ,  Hyun Cheol BAE ,  Sang Heung LEE

Inventor： Sang Hun KIM ,  Hyun Cheol BAE ,  Sang Heung LEE

IPC: H01L29/737 ,  H01L21/331

CPC classification number: H01L29/7378 ,  H01L29/0821 ,  H01L29/66242

Abstract: Provided are a SiGe semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a buried collector by doping impurity ions into a buried collector region formed on a substrate; forming a collector layer which is an active region and a collector electrode region by forming a Si epitaxial layer on the substrate having the buried collector; forming an isolation layer on the substrate and exposing the collector layer and the collector electrode region; forming a collector pad oxide layer on the collector electrode region; stacking a base epitaxial layer and a pad oxide layer on the substrate having the collector pad oxide layer and patterning the pad oxide layer; forming a first polycrystalline Si (poly-Si) layer on the patterned pad oxide layer; exposing at least a portion of the patterned pad oxide layer by etching the first poly-Si layer; depositing a metal layer on the first poly-Si layer to form a first silicide layer; forming an oxide layer on the substrate having the first silicide layer, and exposing a base-emitter junction and the collector electrode region; forming an emitter electrode and a collector electrode by depositing a second poly-Si layer on the exposed base-emitter junction and collector electrode region; and depositing a metal layer on the emitter and collector electrodes to form a second silicide layer, and forming a base terminal, an emitter terminal, and a collector terminal. In this method, base parasitic resistance can be reduced, an electrical short due to agglomeration caused by Ge can be prevented during the formation of the silicide layer, and the base-emitter junction can be protected using the pad oxide layer from external processes, thereby enhancing process stability and reliability.

Abstract translation: 提供了一种SiGe半导体器件及其制造方法。 该方法包括以下步骤：通过将杂质离子掺杂到形成在衬底上的掩埋集电区中来形成掩埋集电极; 通过在具有该埋设集电体的基板上形成Si外延层，形成作为有源区和集电极区的集电极层; 在所述基板上形成隔离层并使所述集电极层和所述集电极区域露出; 在集电极区域上形成集电极氧化层; 在具有集电极衬垫氧化物层的衬底上堆叠基极外延层和焊盘氧化物层，并对衬垫氧化物层进行构图; 在所述图案化衬垫氧化物层上形成第一多晶Si（多晶硅）层; 通过蚀刻第一多晶硅层来暴露图案化的衬垫氧化物层的至少一部分; 在所述第一多晶硅层上沉积金属层以形成第一硅化物层; 在具有第一硅化物层的衬底上形成氧化物层，并暴露出基极 - 发射极结和集电极区域; 通过在暴露的基极 - 发射极结和集电极区域上沉积第二多晶硅层来形成发射极和集电极; 以及在所述发射极和集电极上沉积金属层以形成第二硅化物层，以及形成基极端子，发射极端子和集电极端子。 在该方法中，可以降低基极寄生电阻，在硅化物层的形成期间可以防止由Ge引起的聚集引起的电短路，并且可以使用衬垫氧化物层从外部工艺来保护基极 - 发射极结，从而 提高工艺稳定性和可靠性。

公开(公告)号：US07303966B2

公开(公告)日：2007-12-04

申请号：US11485895

申请日：2006-07-13

Applicant: Sang Hun Kim ,  Hyun Cheol Bae ,  Sang Heung Lee

Inventor： Sang Hun Kim ,  Hyun Cheol Bae ,  Sang Heung Lee

IPC: H01L21/336

CPC classification number: H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/78 ,  H01L29/7848

Abstract: Provided are a semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a first silicon layer on a semiconductor substrate; patterning the first silicon layer formed on the semiconductor substrate, and exposing a channel region; forming a second silicon layer on the semiconductor substrate in which the channel region is exposed; removing the first silicon layer, and forming source and drain regions; and forming a third silicon layer in the source and drain regions. According to the manufacturing method, it is possible to minimize defects in a silicon interface by forming the source and drain using only a selective epitaxial growth method without a dry-etching process. Also, since stress is concentrated to a silicon channel region, hole mobility and driving current characteristics are considerably improved.

公开(公告)号：US07157977B2

公开(公告)日：2007-01-02

申请号：US10995033

申请日：2004-11-23

Applicant: Sang Heung Lee ,  Hyeon Cheol Ki ,  Jin Yeong Kang ,  Kyu Hwan Shim ,  Kyong Ik Cho

Inventor： Sang Heung Lee ,  Hyeon Cheol Ki ,  Jin Yeong Kang ,  Kyu Hwan Shim ,  Kyong Ik Cho

IPC: H03F3/08

CPC classification number: H03F3/08 ,  H03F1/34 ,  H03F3/3432 ,  H03F3/50 ,  H03G3/3084

Abstract: There is provided a feedback amplifier capable of easily controlling its dynamic range without a separate gain control signal generation circuit. The feedback amplifier includes an input terminal detecting an input voltage from input current, a feedback amplification unit amplifying the input voltage to generate an output signal, and an output terminal outputting a signal amplified by the feedback amplification unit. The feedback amplification unit includes a feedback circuit unit including a feedback resistor located between the input terminal and the output terminal, and a feedback transistor connected in parallel to the feedback resistor; and a bias circuit unit supplying a predetermined bias voltage to the feedback transistor of the feedback circuit unit and merged in the feedback amplification unit.

Abstract translation: 提供了一种反馈放大器，其能够在没有单独的增益控制信号产生电路的情况下容易地控制其动态范围。 反馈放大器包括检测来自输入电流的输入电压的输入端子，放大输入电压以产生输出信号的反馈放大单元，以及输出由反馈放大单元放大的信号的输出端子。 反馈放大单元包括反馈电路单元，该反馈电路单元包括位于输入端子和输出端子之间的反馈电阻器和与反馈电阻器并联连接的反馈晶体管; 以及偏置电路单元，向反馈电路单元的反馈晶体管提供预定的偏置电压并且合并在反馈放大单元中。

公开(公告)号：US20120153361A1

公开(公告)日：2012-06-21

申请号：US13307069

申请日：2011-11-30

Applicant: Hokyun Ahn ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Byoung-Gue Min ,  Sang-Heung Lee ,  Hae Cheon Kim ,  Eun Soo Nam

Inventor： Hokyun Ahn ,  Jong-Won Lim ,  Hyung Sup Yoon ,  Byoung-Gue Min ,  Sang-Heung Lee ,  Hae Cheon Kim ,  Eun Soo Nam

IPC: H01L21/283 ,  H01L29/808

CPC classification number: H01L29/7831 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/66863 ,  H01L29/7787 ,  H01L29/812

Abstract: Disclosed are a field-effect transistor and a manufacturing method thereof. The disclosed field-effect transistor includes: a semiconductor substrate; a source ohmic metal layer formed on one side of the semiconductor substrate; a drain ohmic metal layer formed on another side of the semiconductor substrate; a gate electrode formed between the source ohmic metal layer and the drain ohmic metal layer, on an upper portion of the semiconductor substrate; an insulating film formed on the semiconductor substrate's upper portion including the source ohmic metal layer, the drain ohmic metal layer and the gate electrode; and a plurality of field electrodes formed on an upper portion of the insulating film, wherein the insulating film below the respective field electrodes has different thicknesses.

Abstract translation: 公开了场效应晶体管及其制造方法。 所公开的场效应晶体管包括：半导体衬底; 源极欧姆金属层，形成在半导体衬底的一侧上; 形成在所述半导体衬底的另一侧上的漏极欧姆金属层; 在所述源极欧姆金属层和所述漏极欧姆金属层之间形成的栅电极，位于所述半导体衬底的上部; 形成在包括源极欧姆金属层，漏极欧姆金属层和栅电极的半导体衬底的上部上的绝缘膜; 以及形成在绝缘膜的上部的多个场电极，其中，各个场电极下方的绝缘膜具有不同的厚度。

公开(公告)号：US20120142148A1

公开(公告)日：2012-06-07

申请号：US13283626

申请日：2011-10-28

Applicant: Hyung Sup YOON ,  Byoung-Gue Min ,  Hokyun Ahn ,  Sang-Heung Lee ,  Hae Cheon Kim

Inventor： Hyung Sup YOON ,  Byoung-Gue Min ,  Hokyun Ahn ,  Sang-Heung Lee ,  Hae Cheon Kim

IPC: H01L21/335

CPC classification number: H01L29/7783 ,  H01L21/8252 ,  H01L27/0605 ,  H01L29/42316 ,  H01L29/66462

Abstract: Provided are a method of manufacturing a normally-off mode high frequency device structure and a method of simultaneously manufacturing a normally-on mode high frequency device structure and a normally-off mode high frequency device structure on a single substrate.

Abstract translation: 提供一种制造常闭型高频器件结构的方法以及在单个衬底上同时制造常开模式高频器件结构和常关型高频器件结构的方法。

公开(公告)号：US07550796B2

公开(公告)日：2009-06-23

申请号：US11947123

申请日：2007-11-29

Applicant: Sang Hun Kim ,  Hyun Cheol Bae ,  Sang Heung Lee

Inventor： Sang Hun Kim ,  Hyun Cheol Bae ,  Sang Heung Lee

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/66613 ,  H01L21/223 ,  H01L21/28079 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/78684

Abstract: A germanium semiconductor device and a method of manufacturing the same are provided. The method includes the steps of: forming an isolation layer on a substrate using a shallow trench; forming a silicon-nitride layer on the substrate, and selectively etching the silicon nitride layer to expose source and drain regions; injecting impurities onto a surface of the substrate over the exposed source and drain regions using delta-doping to form a delta-doping layer; selectively growing a silicon germanium layer containing impurities on the delta-doping layer; rapidly annealing the substrate and forming source and drain regions by diffusion of the impurities; depositing an insulating layer on the entire surface of the substrate; etching the insulating layer and forming source and drain contact parts to be in contact with source and drain terminals; depositing metal over the insulating layer having the source and drain contact parts thereon and forming a metal silicide layer; and after forming the silicide layer, forming the source and drain terminals to be in contact with the silicide layer. Accordingly, the source and drain regions having a shallow junction depth may be ensured by forming the source and drain regions through annealing after delta-doping and selectively growing the silicon germanium layer containing high-concentration impurities. Also, the germanium silicide layer is stably formed by the silicon germanium layer grown in the source and drain regions, and thus contact resistance is lowered and driving current of the device is improved.

Abstract translation: 提供锗半导体器件及其制造方法。 该方法包括以下步骤：使用浅沟槽在衬底上形成隔离层; 在衬底上形成氮化硅层，并选择性地蚀刻氮化硅层以暴露出源区和漏区; 使用增量掺杂在暴露的源极和漏极区域上在衬底的表面上注入杂质以形成δ-掺杂层; 在δ-掺杂层上选择性地生长含有杂质的硅锗层; 快速退火衬底并通过杂质扩散形成源区和漏区; 在基板的整个表面上沉积绝缘层; 蚀刻绝缘层并形成源极和漏极接触部分以与源极和漏极端子接触; 在其上具有源极和漏极接触部分的绝缘层上沉积金属并形成金属硅化物层; 并且在形成硅化物层之后，形成与硅化物层接触的源极和漏极端子。 因此，具有浅结深度的源极和漏极区域可以通过在增量掺杂之后退火形成源区和漏极区域并选择性地生长含有高浓度杂质的硅锗层来确保。 此外，通过在源极区和漏极区中生长的硅锗层稳定地形成硅化锗层，因此接触电阻降低，器件的驱动电流提高。

公开(公告)号：US20090134944A1

公开(公告)日：2009-05-28

申请号：US12114705

申请日：2008-05-02

Applicant: Ja Yol Lee ,  Sang Heung Lee ,  Hae Cheon Kim ,  Hyun Kyu Yu

Inventor： Ja Yol Lee ,  Sang Heung Lee ,  Hae Cheon Kim ,  Hyun Kyu Yu

IPC: H03B5/12

CPC classification number: H03B5/1231 ,  H03B5/1212 ,  H03B5/1215 ,  H03B5/1221 ,  H03B5/1253

Abstract: A capacitive-degeneration double cross-coupled voltage-controlled oscillator is provided. The capacitive-degeneration double cross-coupled voltage-controlled oscillator includes a main cross-coupled oscillating unit including an oscillation transistor pair cross-coupled to first and second output nodes of a resonating unit to perform an oscillation operation; and an auxiliary cross-coupled oscillating unit including a positive-feedback transistor pair cross-coupled to the first and second output nodes and the transistor pair of the main cross-coupled oscillating unit and a degeneration capacitance connected between emitters of the positive-feedback transistor pair so as to increase a negative resistance of the main cross-coupled oscillating unit. Accordingly, it is possible to increase a maximum attainable oscillation frequency and to decrease an input capacitance.

Abstract translation: 提供电容变性双交叉耦合压控振荡器。 电容变性双交叉电压控制振荡器包括主交叉耦合振荡单元，其包括交叉耦合到谐振单元的第一和第二输出节点的振荡晶体管对，以执行振荡操作; 以及辅助交叉耦合振荡单元，其包括交叉耦合到第一和第二输出节点的正反馈晶体管对和主交叉耦合振荡单元的晶体管对，以及连接在正反馈晶体管的发射极之间的退化电容 以增加主交叉振荡单元的负电阻。 因此，可以增加最大可获得的振荡频率并降低输入电容。