公开(公告)号：US20080128754A1

公开(公告)日：2008-06-05

申请号：US11947098

申请日：2007-11-29

Applicant: Sang Hun KIM ,  Hyun Cheol BAE ,  Sang Heung LEE

Inventor： Sang Hun KIM ,  Hyun Cheol BAE ,  Sang Heung LEE

IPC: H01L29/737 ,  H01L21/331

CPC classification number: H01L29/7378 ,  H01L29/0821 ,  H01L29/66242

Abstract: Provided are a SiGe semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a buried collector by doping impurity ions into a buried collector region formed on a substrate; forming a collector layer which is an active region and a collector electrode region by forming a Si epitaxial layer on the substrate having the buried collector; forming an isolation layer on the substrate and exposing the collector layer and the collector electrode region; forming a collector pad oxide layer on the collector electrode region; stacking a base epitaxial layer and a pad oxide layer on the substrate having the collector pad oxide layer and patterning the pad oxide layer; forming a first polycrystalline Si (poly-Si) layer on the patterned pad oxide layer; exposing at least a portion of the patterned pad oxide layer by etching the first poly-Si layer; depositing a metal layer on the first poly-Si layer to form a first silicide layer; forming an oxide layer on the substrate having the first silicide layer, and exposing a base-emitter junction and the collector electrode region; forming an emitter electrode and a collector electrode by depositing a second poly-Si layer on the exposed base-emitter junction and collector electrode region; and depositing a metal layer on the emitter and collector electrodes to form a second silicide layer, and forming a base terminal, an emitter terminal, and a collector terminal. In this method, base parasitic resistance can be reduced, an electrical short due to agglomeration caused by Ge can be prevented during the formation of the silicide layer, and the base-emitter junction can be protected using the pad oxide layer from external processes, thereby enhancing process stability and reliability.

Abstract translation: 提供了一种SiGe半导体器件及其制造方法。 该方法包括以下步骤：通过将杂质离子掺杂到形成在衬底上的掩埋集电区中来形成掩埋集电极; 通过在具有该埋设集电体的基板上形成Si外延层，形成作为有源区和集电极区的集电极层; 在所述基板上形成隔离层并使所述集电极层和所述集电极区域露出; 在集电极区域上形成集电极氧化层; 在具有集电极衬垫氧化物层的衬底上堆叠基极外延层和焊盘氧化物层，并对衬垫氧化物层进行构图; 在所述图案化衬垫氧化物层上形成第一多晶Si（多晶硅）层; 通过蚀刻第一多晶硅层来暴露图案化的衬垫氧化物层的至少一部分; 在所述第一多晶硅层上沉积金属层以形成第一硅化物层; 在具有第一硅化物层的衬底上形成氧化物层，并暴露出基极 - 发射极结和集电极区域; 通过在暴露的基极 - 发射极结和集电极区域上沉积第二多晶硅层来形成发射极和集电极; 以及在所述发射极和集电极上沉积金属层以形成第二硅化物层，以及形成基极端子，发射极端子和集电极端子。 在该方法中，可以降低基极寄生电阻，在硅化物层的形成期间可以防止由Ge引起的聚集引起的电短路，并且可以使用衬垫氧化物层从外部工艺来保护基极 - 发射极结，从而 提高工艺稳定性和可靠性。

公开(公告)号：US20080135878A1

公开(公告)日：2008-06-12

申请号：US11947123

申请日：2007-11-29

Applicant: Sang Hun KIM ,  Hyun Cheol BAE ,  Sang Heung LEE

Inventor： Sang Hun KIM ,  Hyun Cheol BAE ,  Sang Heung LEE

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66613 ,  H01L21/223 ,  H01L21/28079 ,  H01L29/165 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/66742 ,  H01L29/78 ,  H01L29/78684

Abstract: A germanium semiconductor device and a method of manufacturing the same are provided. The method includes the steps of: forming an isolation layer on a substrate using a shallow trench; forming a silicon-nitride layer on the substrate, and selectively etching the silicon nitride layer to expose source and drain regions; injecting impurities onto a surface of the substrate over the exposed source and drain regions using delta-doping to form a delta-doping layer; selectively growing a silicon germanium layer containing impurities on the delta-doping layer; rapidly annealing the substrate and forming source and drain regions by diffusion of the impurities; depositing an insulating layer on the entire surface of the substrate; etching the insulating layer and forming source and drain contact parts to be in contact with source and drain terminals; depositing metal over the insulating layer having the source and drain contact parts thereon and forming a metal silicide layer; and after forming the silicide layer, forming the source and drain terminals to be in contact with the silicide layer. Accordingly, the source and drain regions having a shallow junction depth may be ensured by forming the source and drain regions through annealing after delta-doping and selectively growing the silicon germanium layer containing high-concentration impurities. Also, the germanium silicide layer is stably formed by the silicon germanium layer grown in the source and drain regions, and thus contact resistance is lowered and driving current of the device is improved.

Abstract translation: 提供锗半导体器件及其制造方法。 该方法包括以下步骤：使用浅沟槽在衬底上形成隔离层; 在衬底上形成氮化硅层，并选择性地蚀刻氮化硅层以暴露出源区和漏区; 使用增量掺杂在暴露的源极和漏极区域上在衬底的表面上注入杂质以形成δ-掺杂层; 在δ-掺杂层上选择性地生长含有杂质的硅锗层; 快速退火衬底并通过杂质扩散形成源区和漏区; 在基板的整个表面上沉积绝缘层; 蚀刻绝缘层并形成源极和漏极接触部分以与源极和漏极端子接触; 在其上具有源极和漏极接触部分的绝缘层上沉积金属并形成金属硅化物层; 并且在形成硅化物层之后，形成与硅化物层接触的源极和漏极端子。 因此，具有浅结深度的源极和漏极区域可以通过在增量掺杂之后退火形成源区和漏极区域并选择性地生长含有高浓度杂质的硅锗层来确保。 此外，通过在源极区和漏极区中生长的硅锗层稳定地形成硅化锗层，因此接触电阻降低，器件的驱动电流提高。