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    CLOCK GENERATOR TO REDUCE LONG TERM JITTER
    21.
    发明申请
    CLOCK GENERATOR TO REDUCE LONG TERM JITTER 有权
    时钟发生器减少长期抖动

    公开(公告)号：US20100244914A1

    公开(公告)日：2010-09-30

    申请号：US12691023

    申请日：2010-01-21

    申请人： Chul-woo Kim ,  Woo-seok Kim ,  Min-young Song ,  Jae-jin Park ,  Ji-hyun Kim ,  Young-ho Kwak

    发明人： Chul-woo Kim ,  Woo-seok Kim ,  Min-young Song ,  Jae-jin Park ,  Ji-hyun Kim ,  Young-ho Kwak

    IPC分类号： H03L7/06

    CPC分类号： H03L7/23 ,  H03L7/085 ,  H03L7/0991 ,  H03L7/1075 ,  H03L2207/06 ,  H03L2207/50

    摘要： A clock generator includes a controller, a digital phase locked loop (PLL) circuit, a charge pump phase locked loop (PLL) circuit and a divider. The controller generates a division factor and a first internal clock signal in response to a low-frequency reference clock signal and a multiplication factor. The digital PLL circuit generates a second internal clock signal in response to the reference clock signal, the division factor and the first internal clock signal. The charge pump PLL circuit generates a plurality of third internal clock signals by using the second internal clock signal. The divider generates a high-frequency clock signal in response to a phase selection signal, the division factor and the third internal clock signals.

    摘要翻译： 时钟发生器包括控制器，数字锁相环（PLL）电路，电荷泵锁相环（PLL）电路和分频器。 响应于低频参考时钟信号和乘法因子，控制器产生除法系数和第一内部时钟信号。 数字PLL电路响应于参考时钟信号，分频因子和第一内部时钟信号产生第二内部时钟信号。 电荷泵PLL电路通过使用第二内部时钟信号产生多个第三内部时钟信号。 分频器响应于相位选择信号，分频因子和第三内部时钟信号产生高频时钟信号。

    LINEAR PHASE DETECTOR AND CLOCK/DATA RECOVERY CIRCUIT THEREOF
    23.
    发明申请
    LINEAR PHASE DETECTOR AND CLOCK/DATA RECOVERY CIRCUIT THEREOF 有权
    线性相位检测器及其时钟/数据恢复电路

    公开(公告)号：US20080049884A1

    公开(公告)日：2008-02-28

    申请号：US11843785

    申请日：2007-08-23

    申请人： Chul-Woo KIM ,  Seok-Soo YOON ,  Young-Ho KWAK ,  In-Ho LEE ,  Ki-Hong KIM

    发明人： Chul-Woo KIM ,  Seok-Soo YOON ,  Young-Ho KWAK ,  In-Ho LEE ,  Ki-Hong KIM

    IPC分类号： H03D3/24

    CPC分类号： H03L7/087 ,  H03D13/00 ,  H03L7/0891

    摘要： A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.

    摘要翻译： 线性相位检测器包括响应于接收的数据信号和恢复的时钟信号而工作的上/下脉冲发生器。 相位检测器产生具有与接收的数据信号的转变和恢复的时钟信号的边沿之间的相位差成比例的脉冲宽度的上升和下降脉冲。 通过使用与相位误差成比例的线性相位检测器产生上升和下降脉冲，数据信号被有效地恢复，甚至具有显着抖动的数据信号。

    Delayed clock signal generator
    24.
    发明授权
    Delayed clock signal generator 有权
    延时时钟信号发生器

    公开(公告)号：US07106117B2

    公开(公告)日：2006-09-12

    申请号：US10910644

    申请日：2004-08-04

    申请人： Gun-Ok Jung ,  Jin-Han Kim ,  Sung-Bae Park ,  Chul-Woo Kim ,  Seok-Soo Yoon ,  Seok-Ryoung Yoon

    发明人： Gun-Ok Jung ,  Jin-Han Kim ,  Sung-Bae Park ,  Chul-Woo Kim ,  Seok-Soo Yoon ,  Seok-Ryoung Yoon

    IPC分类号： H03H11/26

    CPC分类号： H03K5/133 ,  H03K5/135 ,  H03K2005/00156 ,  H03K2005/00286

    摘要： A device which may be configured to generate delayed clock signals by a specified phase difference, which may include a clock generator circuit for generating at least one clock signal, a delayed clock signal generator for delaying the at least one clock signal, a phase detect circuit for generating a selecting signal based on the amount of phase delay detected according to a half-cycle (π), and in comparison with the clock signal, a phase interpolation circuit for controlling the delay time of the delayed clock signals and interpolating the delayed clock signals, and a selecting circuit which outputs the delayed clock signal delayed by a specified phase difference.

    摘要翻译： 一种可被配置为通过指定的相位差产生延迟的时钟信号的装置，其可以包括用于产生至少一个时钟信号的时钟发生器电路，用于延迟所述至少一个时钟信号的延迟时钟信号发生器，相位检测电路 用于基于根据半周期（pi）检测到的相位延迟量来生成选择信号，并且与时钟信号相比，相位插值电路用于控制延迟的时钟信号的延迟时间并内插延迟的时钟 信号，以及输出延迟了指定相位差的延迟时钟信号的选择电路。

    Method for reliably managing database in GSM/GPRS hybrid terminal and hybrid terminal
    25.
    发明申请
    Method for reliably managing database in GSM/GPRS hybrid terminal and hybrid terminal 有权
    GSM / GPRS混合终端和混合终端可靠管理数据库的方法

    公开(公告)号：US20060105807A1

    公开(公告)日：2006-05-18

    申请号：US11230966

    申请日：2005-09-20

    申请人： Chul-Woo Kim

    发明人： Chul-Woo Kim

    IPC分类号： H04M1/00

    CPC分类号： G06F1/1613 ,  H04M1/2745 ,  H04M1/72522 ,  H04M1/72527

    摘要： Disclosed is a hybrid terminal, which includes a mobile terminal unit for a Global System for Mobile communication (GSM) or a General Packet Radio Service (GPRS), a PDA (Personal Digital Assistant) unit combined with the mobile terminal unit, and a mirror database being connected between the mobile terminal and the PDA, for providing a memory space required for operations of the mobile terminal and the PDA, wherein the PDA includes a database for storing PDA data, reads the PDA data, and stores the read PDA data in the mirror database, wherein the mobile terminal includes a Subscriber Identity Module (SIM) card for storing SIM data, reads the SIM data, and stores the read SIM data in the mirror database.

    摘要翻译： 公开了一种混合终端，其包括用于全球移动通信系统（GSM）或通用分组无线业务（GPRS）的移动终端单元，与移动终端单元组合的PDA（个人数字助理）单元和镜 数据库连接在移动终端和PDA之间，用于提供移动终端和PDA的操作所需的存储器空间，其中PDA包括用于存储PDA数据的数据库，读取PDA数据，并将读取的PDA数据存储在 镜像数据库，其中移动终端包括用于存储SIM卡数据的用户识别模块（SIM）卡，读取SIM数据，并将读取的SIM数据存储在镜像数据库中。

    Image display device having slim type cathode ray tube
    26.
    发明申请
    Image display device having slim type cathode ray tube 审中-公开
    具有超薄型阴极射线管的图像显示装置

    公开(公告)号：US20060017859A1

    公开(公告)日：2006-01-26

    申请号：US11153033

    申请日：2005-06-14

    申请人： Han-Wook Choi ,  Chul-Woo Kim

    发明人： Han-Wook Choi ,  Chul-Woo Kim

    IPC分类号： H04N5/645

    CPC分类号： H04N5/645

    摘要： An image display device includes a cathode ray tube for displaying images, a case enclosing the cathode ray tube while forming the outer appearance thereof, and a support partially receiving the cathode ray tube and connected to the case to support the case. The support includes: a post, with one end portion connected to the case, a support portion tightly fitted to the case to support the case, and a portion proceeding substantially vertical to the ground surface; and a base connected to the post to stand the post erect.

    摘要翻译： 图像显示装置包括用于显示图像的阴极射线管，包围阴极射线管同时形成外观的外壳，以及部分地容纳阴极射线管并与壳体连接以支撑外壳的支撑件。 支撑件包括：一端部，其一端连接到壳体，一紧固于壳体的支撑部分以支撑壳体;以及基本垂直于地表面延伸的部分; 和连接到柱子的基座直立立柱。

    Method for tracing optimal path using Trellis-based adaptive quantizer
    27.
    发明授权
    Method for tracing optimal path using Trellis-based adaptive quantizer 有权
    使用基于网格的自适应量化器跟踪最优路径的方法

    公开(公告)号：US06697434B1

    公开(公告)日：2004-02-24

    申请号：US09487226

    申请日：2000-01-19

    申请人： Chul Woo Kim

    发明人： Chul Woo Kim

    IPC分类号： H04B1406

    CPC分类号： H04N19/19 ,  H04N19/126 ,  H04N19/147 ,  H04N19/176 ,  H04N19/60 ,  H04N19/61

    摘要： A method for tracing an optimal path by employing a Trellis-based adaptive quantizer can accelerate quantization path tracing and simplify computation thereof, by preventing the quantization path tracing after an turning point of distortion in the Trellis-based adaptive quantizer and after an optimal quantization level to non-zero at a branch positioned from a zero node to a non-zero node. The conventional Trellis-based adaptive quantizer selects the optimal path by tracing and examining all the paths, and thus computation is complicated. In addition, a high speed quantization algorithm is difficult to perform. According to the present invention, in a Trellis-based adaptive quantizer of Trellis run length coding and entropy constraining coefficients generated by performing discrete cosine transformation (DCT) on image signals in block units, a method for tracing an optimal path by employing a Trellis-based adaptive quantizer, includes: a step for preventing quantization path tracing of branches after a variation position of distortion, on the basis of arrangement of a quantization period and monotonic increasing of a code word length, in a Trellis structure of generating one stage whenever the coefficients are quantized one by one from a predetermined node; and a step for preventing path tracing after an optimal coding level to non-zero at the branches positioned from zero to non-zero, based on independence of the respective stages, when quantizing non-zero coefficients from the predetermined node.

    摘要翻译： 通过采用基于网格的自适应量化器来跟踪最佳路径的方法可以通过防止在基于网格的自适应量化器中的失真转折点之后并且在最佳量化级之后的量化路径跟踪来加速量化路径跟踪并简化其计算 在从零节点到非零节点的分支处非零。 传统的基于网格的自适应量化器通过跟踪和检查所有路径来选择最优路径，从而计算复杂。 此外，难以执行高速量化算法。 根据本发明，在通过以块为单位对图像信号执行离散余弦变换（DCT）而产生的网格游程长度编码和熵约束系数的基于网格的自适应量化器中，通过采用网格轨迹追踪最佳路径的方法， 基于自适应量化器的步骤包括：根据量化周期的配置和代码字长度的单调增加来防止在失真的变化位置之后的分支的量化路径跟踪的步骤，每当产生一个阶段的网格结构 系数从预定节点逐个量化; 以及当从所述预定节点量化非零系数时，基于各个级的独立性，在从零到非零的分支的最优编码电平到非零之后防止路径跟踪的步骤。

    Kelp chip manufacturing method
    28.
    发明授权
    Kelp chip manufacturing method 有权

    公开(公告)号：US10004252B2

    公开(公告)日：2018-06-26

    申请号：US14922984

    申请日：2015-10-26

    申请人： Chul-Woo Kim

    发明人： Chul-Woo Kim

    IPC分类号： A23L17/60 ,  A23L5/10 ,  A23L3/44

    CPC分类号： A23L17/60 ,  A23B7/024 ,  A23L3/44 ,  A23L5/11

    摘要： Provided is a kelp chip manufacturing method which does not require frying with no transformation of the shape of kelp but has high preference. The kelp chip manufacturing method includes: a kelp braizing process of braizing kelp using one of starch syrup, soy source, olive oil or mixture of starch syrup, soy source and olive oil; a kelp heating process of heating the braized kelp in a retort-pouched state; and a kelp freeze-drying process of freeze-drying the heated kelp. The kelp chip manufacturing method can manufacture kelp chips with high preference in texture, taste and so on through the kelp braizing process and the kelp heating process.