公开(公告)号：US20100244914A1

公开(公告)日：2010-09-30

申请号：US12691023

申请日：2010-01-21

Applicant: Chul-woo Kim ,  Woo-seok Kim ,  Min-young Song ,  Jae-jin Park ,  Ji-hyun Kim ,  Young-ho Kwak

Inventor： Chul-woo Kim ,  Woo-seok Kim ,  Min-young Song ,  Jae-jin Park ,  Ji-hyun Kim ,  Young-ho Kwak

IPC: H03L7/06

CPC classification number: H03L7/23 ,  H03L7/085 ,  H03L7/0991 ,  H03L7/1075 ,  H03L2207/06 ,  H03L2207/50

Abstract: A clock generator includes a controller, a digital phase locked loop (PLL) circuit, a charge pump phase locked loop (PLL) circuit and a divider. The controller generates a division factor and a first internal clock signal in response to a low-frequency reference clock signal and a multiplication factor. The digital PLL circuit generates a second internal clock signal in response to the reference clock signal, the division factor and the first internal clock signal. The charge pump PLL circuit generates a plurality of third internal clock signals by using the second internal clock signal. The divider generates a high-frequency clock signal in response to a phase selection signal, the division factor and the third internal clock signals.

Abstract translation: 时钟发生器包括控制器，数字锁相环（PLL）电路，电荷泵锁相环（PLL）电路和分频器。 响应于低频参考时钟信号和乘法因子，控制器产生除法系数和第一内部时钟信号。 数字PLL电路响应于参考时钟信号，分频因子和第一内部时钟信号产生第二内部时钟信号。 电荷泵PLL电路通过使用第二内部时钟信号产生多个第三内部时钟信号。 分频器响应于相位选择信号，分频因子和第三内部时钟信号产生高频时钟信号。

公开(公告)号：US20080049884A1

公开(公告)日：2008-02-28

申请号：US11843785

申请日：2007-08-23

Applicant: Chul-Woo KIM ,  Seok-Soo YOON ,  Young-Ho KWAK ,  In-Ho LEE ,  Ki-Hong KIM

Inventor： Chul-Woo KIM ,  Seok-Soo YOON ,  Young-Ho KWAK ,  In-Ho LEE ,  Ki-Hong KIM

IPC: H03D3/24

CPC classification number: H03L7/087 ,  H03D13/00 ,  H03L7/0891

Abstract: A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.

Abstract translation: 线性相位检测器包括响应于接收的数据信号和恢复的时钟信号而工作的上/下脉冲发生器。 相位检测器产生具有与接收的数据信号的转变和恢复的时钟信号的边沿之间的相位差成比例的脉冲宽度的上升和下降脉冲。 通过使用与相位误差成比例的线性相位检测器产生上升和下降脉冲，数据信号被有效地恢复，甚至具有显着抖动的数据信号。

公开(公告)号：US08451970B2

公开(公告)日：2013-05-28

申请号：US13035093

申请日：2011-02-25

Applicant: Chul Woo Kim ,  Young Ho Kwak

Inventor： Chul Woo Kim ,  Young Ho Kwak

IPC: H03D3/24 ,  H04L7/00 ,  H04L25/40 ,  H03L7/06 ,  H03L7/00

CPC classification number: H04L7/00

Abstract: The present disclosure provides a variable delay circuit comprising a delay circuit that includes a first delay unit and a second delay unit and delays an input signal to generate an output signal; a selection signal generation unit that detects a delay value of the delay circuit and generates a selection signal to select a delay unit for delaying the input signal from the first delay unit and the second delay unit; a first control unit that controls a delay value of the delay unit selected by the selection signal in response to a delay increase/decrease signal; and a second control unit that controls a delay value of the delay unit which is not selected by the selection signal.

Abstract translation: 本公开提供了一种可变延迟电路，包括延迟电路，该延迟电路包括第一延迟单元和第二延迟单元，并延迟输入信号以产生输出信号; 选择信号生成单元，其检测所述延迟电路的延迟值，并生成选择信号，以选择用于延迟来自所述第一延迟单元和所述第二延迟单元的输入信号的延迟单元; 第一控制单元，响应于延迟增减信号，控制由选择信号选择的延迟单元的延迟值; 以及第二控制单元，其控制未被选择信号选择的延迟单元的延迟值。

公开(公告)号：US08149030B2

公开(公告)日：2012-04-03

申请号：US12691023

申请日：2010-01-21

Applicant: Chul-woo Kim ,  Woo-seok Kim ,  Min-young Song ,  Jae-jin Park ,  Ji-hyun Kim ,  Young-ho Kwak

Inventor： Chul-woo Kim ,  Woo-seok Kim ,  Min-young Song ,  Jae-jin Park ,  Ji-hyun Kim ,  Young-ho Kwak

IPC: H03L7/06

CPC classification number: H03L7/23 ,  H03L7/085 ,  H03L7/0991 ,  H03L7/1075 ,  H03L2207/06 ,  H03L2207/50

Abstract: A clock generator includes a controller, a digital phase locked loop (PLL) circuit, a charge pump phase locked loop (PLL) circuit and a divider. The controller generates a division factor and a first internal clock signal in response to a low-frequency reference clock signal and a multiplication factor. The digital PLL circuit generates a second internal clock signal in response to the reference clock signal, the division factor and the first internal clock signal. The charge pump PLL circuit generates a plurality of third internal clock signals by using the second internal clock signal. The divider generates a high-frequency clock signal in response to a phase selection signal, the division factor and the third internal clock signals.

Abstract translation: 时钟发生器包括控制器，数字锁相环（PLL）电路，电荷泵锁相环（PLL）电路和分频器。 响应于低频参考时钟信号和乘法因子，控制器产生除法系数和第一内部时钟信号。 数字PLL电路响应于参考时钟信号，分频因子和第一内部时钟信号产生第二内部时钟信号。 电荷泵PLL电路通过使用第二内部时钟信号产生多个第三内部时钟信号。 分频器响应于相位选择信号，分频因子和第三内部时钟信号产生高频时钟信号。

公开(公告)号：US20110228887A1

公开(公告)日：2011-09-22

申请号：US13152497

申请日：2011-06-03

Applicant: Chul-Woo KIM ,  Seok-Soo YOON ,  Young-Ho KWAK ,  In-Ho LEE ,  Ki-Hong KIM

Inventor： Chul-Woo KIM ,  Seok-Soo YOON ,  Young-Ho KWAK ,  In-Ho LEE ,  Ki-Hong KIM

IPC: H04L7/02

CPC classification number: H03L7/087 ,  H03D13/00 ,  H03L7/0891

Abstract: A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.

Abstract translation: 线性相位检测器包括响应于接收的数据信号和恢复的时钟信号而工作的上/下脉冲发生器。 相位检测器产生具有与接收的数据信号的转变和恢复的时钟信号的边沿之间的相位差成比例的脉冲宽度的上升和下降脉冲。 通过使用与相位误差成比例的线性相位检测器产生上升和下降脉冲，数据信号被有效地恢复，甚至具有显着抖动的数据信号。

公开(公告)号：US07974375B2

公开(公告)日：2011-07-05

申请号：US11843785

申请日：2007-08-23

Applicant: Chul-Woo Kim ,  Seok-Soo Yoon ,  Young-Ho Kwak ,  In-Ho Lee ,  Ki-Hong Kim

Inventor： Chul-Woo Kim ,  Seok-Soo Yoon ,  Young-Ho Kwak ,  In-Ho Lee ,  Ki-Hong Kim

IPC: H03D3/24

CPC classification number: H03L7/087 ,  H03D13/00 ,  H03L7/0891

Abstract: A linear phase detector includes an up/down pulse generator operating in response to received data signals and a recovered clock signal. The phase detector generates up and down pulses that have pulse widths proportional to the phase differences between transitions of the received data signals and edges of the recovered clock signal. By generating up and down pulses using a linear phase detector in proportion to a phase error, data signals are effectively recovered, even data signals with significant jitter.

Abstract translation: 线性相位检测器包括响应于接收的数据信号和恢复的时钟信号而工作的上/下脉冲发生器。 相位检测器产生具有与接收的数据信号的转变和恢复的时钟信号的边沿之间的相位差成比例的脉冲宽度的上升和下降脉冲。 通过使用与相位误差成比例的线性相位检测器产生上升和下降脉冲，数据信号被有效地恢复，甚至具有显着抖动的数据信号。

公开(公告)号：US07830184B2

公开(公告)日：2010-11-09

申请号：US11659023

申请日：2005-07-27

Applicant: Chul-Woo Kim ,  Jin-Han Kim ,  Seok-Ryung Yoon ,  Young-Ho Kwak ,  Seok-Soo Yoon

Inventor： Chul-Woo Kim ,  Jin-Han Kim ,  Seok-Ryung Yoon ,  Young-Ho Kwak ,  Seok-Soo Yoon

IPC: H03B19/00

CPC classification number: G06F7/68

Abstract: A frequency multiplier is disclosed. A plurality of voltage regulators each regulate levels of voltages at first and second common nodes in response to a corresponding one of input signals from a voltage-controlled delay line. An input buffer charges the first node or discharges the second node in response to a feedback signal. An output buffer regulates a level of a voltage at an output node and outputs a frequency-multiplied clock signal and the feedback signal corresponding to the voltage level of the output node. A discharge circuit discharges the first node before a rising edge of each of the input signals from the voltage-controlled delay line is inputted. A charge circuit charges the second node before the rising edge of each of the input signals from the voltage-controlled delay line is inputted.

Abstract translation: 公开了一种倍频器。 多个电压调节器响应于来自电压控制延迟线的输入信号中的相应一个，调节第一和第二公共节点处的电压电平。 输入缓冲器对第一节点进行充电或响应于反馈信号对第二节点进行放电。 输出缓冲器调节输出节点处的电压电平，并输出倍频时钟信号和对应于输出节点电压电平的反馈信号。 在输入来自压控延迟线的每个输入信号的上升沿之前，放电电路对第一节点放电。 在输入来自压控延迟线的每个输入信号的上升沿之前，充电电路对第二节点充电。

公开(公告)号：US20110216864A1

公开(公告)日：2011-09-08

申请号：US13035093

申请日：2011-02-25

Applicant: Chul Woo Kim ,  Young Ho Kwak

Inventor： Chul Woo Kim ,  Young Ho Kwak

IPC: H04L7/00

CPC classification number: H04L7/00

Abstract: The present disclosure provides a variable delay circuit comprising a delay circuit that includes a first delay unit and a second delay unit and delays an input signal to generate an output signal; a selection signal generation unit that detects a delay value of the delay circuit and generates a selection signal to select a delay unit for delaying the input signal from the first delay unit and the second delay unit; a first control unit that controls a delay value of the delay unit selected by the selection signal in response to a delay increase/decrease signal; and a second control unit that controls a delay value of the delay unit which is not selected by the selection signal.

Abstract translation: 本公开提供了一种可变延迟电路，包括延迟电路，该延迟电路包括第一延迟单元和第二延迟单元，并延迟输入信号以产生输出信号; 选择信号生成单元，其检测所述延迟电路的延迟值，并生成选择信号，以选择用于延迟来自所述第一延迟单元和所述第二延迟单元的输入信号的延迟单元; 第一控制单元，响应于延迟增减信号，控制由选择信号选择的延迟单元的延迟值; 以及第二控制单元，其控制未被选择信号选择的延迟单元的延迟值。

公开(公告)号：US20090189652A1

公开(公告)日：2009-07-30

申请号：US11659023

申请日：2005-07-27

Applicant: Chul-Woo Kim ,  Jin-Han Kim ,  Seok-Ryung Yoon ,  Young-Ho Kwak ,  Seok-Soo Yoon

Inventor： Chul-Woo Kim ,  Jin-Han Kim ,  Seok-Ryung Yoon ,  Young-Ho Kwak ,  Seok-Soo Yoon

IPC: H03B19/00

CPC classification number: G06F7/68

Abstract: A frequency multiplier is disclosed. A plurality of voltage regulators each regulate levels of voltages at first and second common nodes in response to a corresponding one of input signals from a voltage-controlled delay line. An input buffer charges the first node or discharges the second node in response to a feedback signal. An output buffer regulates a level of a voltage at an output node and outputs a frequency-multiplied clock signal and the feedback signal corresponding to the voltage level of the output node. A discharge circuit discharges the first node before a rising edge of each of the input signals from the voltage-controlled delay line is inputted. A charge circuit charges the second node before the rising edge of each of the input signals from the voltage-controlled delay line is inputted.

Abstract translation: 公开了一种倍频器。 多个电压调节器响应于来自电压控制延迟线的输入信号中的相应一个，调节第一和第二公共节点处的电压电平。 输入缓冲器对第一节点进行充电或响应于反馈信号对第二节点进行放电。 输出缓冲器调节输出节点处的电压电平，并输出倍频时钟信号和对应于输出节点电压电平的反馈信号。 在输入来自压控延迟线的每个输入信号的上升沿之前，放电电路对第一节点放电。 在输入来自压控延迟线的每个输入信号的上升沿之前，充电电路对第二节点充电。

公开(公告)号：US20080048904A1

公开(公告)日：2008-02-28

申请号：US11892476

申请日：2007-08-23

Applicant: In-Ho Lee ,  Seok-Soo Yoon ,  Young-Ho Kwak ,  Ki-Hong Kim ,  Chulwoo Kim

Inventor： In-Ho Lee ,  Seok-Soo Yoon ,  Young-Ho Kwak ,  Ki-Hong Kim ,  Chulwoo Kim

IPC: H03L7/06 ,  G08C19/12

CPC classification number: H03L7/095 ,  H03L7/0891 ,  H03L7/0995 ,  H03L7/10

Abstract: A thermometer code generator includes n bit storing stages that are coupled to each other, where n is an integer greater than 1, and the n bit storing stages store a thermometer code, and are adapted to increase the stored thermometer code by 1 in synchronization with a clock signal when an up signal is active, to decrease the stored thermometer code by 1 in synchronization with the clock signal when a down signal is active, and to maintain the stored thermometer code in synchronization with the clock signal when both of the up signal and the down signal are inactive.

Abstract translation: 温度计代码发生器包括相互耦合的n位存储级，其中n是大于1的整数，并且n位存储级存储温度计代码，并且适于将存储的温度计代码增加1，与 当上行信号有效时的时钟信号，当下行信号有效时，与时钟信号同步地将所存储的温度计代码减1，并且当两个上行信号都保持存储的温度计代码与时钟信号同步时 并且下降信号无效。