公开(公告)号：US09081688B2

公开(公告)日：2015-07-14

申请号：US12317801

申请日：2008-12-30

Applicant: Glenn J. Hinton ,  Steven E. Raasch ,  Sebastien Hily ,  John G. Holm ,  Ronak Singhal ,  Avinash Sodani ,  Deborah T. Marr ,  Shubhendu S. Mukherjee ,  Arijit Biswas ,  Adrian C. Moga

Inventor： Glenn J. Hinton ,  Steven E. Raasch ,  Sebastien Hily ,  John G. Holm ,  Ronak Singhal ,  Avinash Sodani ,  Deborah T. Marr ,  Shubhendu S. Mukherjee ,  Arijit Biswas ,  Adrian C. Moga

IPC: G06F12/08

CPC classification number: G06F12/0842 ,  G06F12/0817

Abstract: In one embodiment, the present invention includes a method for providing a cache block in an exclusive state to a first cache and providing the same cache block in the exclusive state to a second cache when cores accessing the two caches are executing redundant threads. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于向第一高速缓存提供处于独占状态的高速缓存块的方法，并且当访问两个高速缓存的核心正在执行冗余线程时，以独占状态将相同的高速缓存块提供给第二高速缓存。 描述和要求保护其他实施例。

公开(公告)号：US08793689B2

公开(公告)日：2014-07-29

申请号：US12797361

申请日：2010-06-09

Applicant: Glenn J. Hinton ,  Steven E. Raasch ,  Avinash Sodani ,  Sebastien Hily ,  John G. Holm ,  Ronak Singhal ,  Deborah T. Marr

Inventor： Glenn J. Hinton ,  Steven E. Raasch ,  Avinash Sodani ,  Sebastien Hily ,  John G. Holm ,  Ronak Singhal ,  Deborah T. Marr

IPC: G06F9/46 ,  G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44

CPC classification number: G06F9/52 ,  G06F9/3851 ,  G06F11/1497 ,  G06F12/1027

Abstract: A redundant multithreading processor is presented. In one embodiment, the processor performs execution of a thread and its duplicate thread in parallel and determines, when in a redundant multithreading mode, whether or not to synchronize an operation of the thread and an operation of the duplicate thread.

Abstract translation: 介绍了冗余多线程处理器。 在一个实施例中，处理器并行执行线程及其重复线程，并且在冗余多线程模式中确定是否同步线程的操作和复制线程的操作。

公开(公告)号：US08521993B2

公开(公告)日：2013-08-27

申请号：US11784864

申请日：2007-04-09

Applicant: Morris Marden ,  Matthew Merten ,  Alexandre Farcy ,  Avinash Sodani ,  James Hadley ,  Ilhyun Kim

Inventor： Morris Marden ,  Matthew Merten ,  Alexandre Farcy ,  Avinash Sodani ,  James Hadley ,  Ilhyun Kim

IPC: G06F9/40

CPC classification number: G06F9/50 ,  G06F9/30101 ,  G06F9/3851 ,  G06F2209/5014

Abstract: A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements in a pipeline away from a processing element associated with a blocking stall to provide fair utilization of the pipeline.

Abstract translation: 这里描述用于在多处理元件环境中提供公平性的方法和装置。 掩模元件被用于具有每个处理元件的保留站的相关部分，同时仍然允许对保留站条目的另一部分的公共访问。 此外，偏置逻辑偏离了管线中的处理元件的选择，远离与阻塞档位相关联的处理元件，以提供管道的公平利用。

公开(公告)号：US20110055524A1

公开(公告)日：2011-03-03

申请号：US12941637

申请日：2010-11-08

Applicant: Morris Marden ,  Matthew Merten ,  Alexandre Farcy ,  Avinash Sodani ,  James Hadley ,  Ilhyun Kim

Inventor： Morris Marden ,  Matthew Merten ,  Alexandre Farcy ,  Avinash Sodani ,  James Hadley ,  Ilhyun Kim

IPC: G06F9/30

CPC classification number: G06F9/50 ,  G06F9/30101 ,  G06F9/3851 ,  G06F2209/5014

Abstract: A method and apparatus for providing fairness in a multi-processing element environment is herein described. Mask elements are utilized to associated portions of a reservation station with each processing element, while still allowing common access to another portion of reservation station entries. Additionally, bias logic biases selection of processing elements in a pipeline away from a processing element associated with a blocking stall to provide fair utilization of the pipeline.

公开(公告)号：US07711898B2

公开(公告)日：2010-05-04

申请号：US10737760

申请日：2003-12-18

Applicant: Avinash Sodani ,  Stephan J. Jourdan ,  Samie B. Samaan

Inventor： Avinash Sodani ,  Stephan J. Jourdan ,  Samie B. Samaan

IPC: G06F12/00

CPC classification number: G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

Abstract: Embodiments of the present invention relate to a system and method for implementing functions of a register translation table of a computer processor, with reduced area requirements as compared to known arrangements. In one embodiment, an apparatus may comprise a register alias table cache to map a logical register to a physical register. The register alias table cache may have a capacity corresponding to a subset of architectural logical registers. The apparatus may further comprise store logic coupled to the cache to perform operations to save an existing content of the physical register if a cache entry corresponding to the logical register is evicted from the cache. The apparatus may also comprise load logic coupled to the cache to perform operations to load a content to the physical register and to form a new entry in the cache if a needed mapping is not present in the cache.

Abstract translation: 本发明的实施例涉及一种用于实现计算机处理器的寄存器转换表的功能的系统和方法，与已知布置相比，其面积要求减小。 在一个实施例中，装置可以包括寄存器别名表高速缓存以将逻辑寄存器映射到物理寄存器。 寄存器别名表缓存可以具有对应于体系结构逻辑寄存器子集的容量。 如果与逻辑寄存器对应的高速缓存条目从高速缓存中逐出，则该设备还可以包括耦合到高速缓存的存储逻辑，以执行操作以保存物理寄存器的现有内容。 该装置还可以包括耦合到高速缓存的负载逻辑，以执行将内容加载到物理寄存器的操作，并且如果高速缓存中不存在必需的映射，则在高速缓存中形成新的条目。

公开(公告)号：US07475225B2

公开(公告)日：2009-01-06

申请号：US11322768

申请日：2005-12-30

Applicant: Stephan J. Jourdan ,  Avinash Sodani ,  Alexandre J. Farcy ,  Per Hammarlund ,  Sebastien Hily ,  Mark C. Davis

Inventor： Stephan J. Jourdan ,  Avinash Sodani ,  Alexandre J. Farcy ,  Per Hammarlund ,  Sebastien Hily ,  Mark C. Davis

IPC: G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/30101 ,  G06F9/3012 ,  G06F9/3828 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3844 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885 ,  G06F9/3891

Abstract: Microarchitecture policies and structures partition execution resource clusters. In disclosed microarchitecture embodiments, micro-operations representing a sequential instruction ordering are partitioned into a two sets. To one set of micro-operations execution resources are allocated from a cluster of execution resources that can perform memory access operations but not branching operations. To the other set of micro-operations execution resources are allocated from a cluster of execution resources that can perform branching operations but not memory access operations. The first and second sets of micro-operations may be executed out of sequential order but are retired to represent their sequential instruction ordering.

Abstract translation: 微架构策略和结构分区执行资源集群。 在公开的微架构实施例中，表示顺序指令排序的微操作被划分成两组。 对于一组微操作执行资源从可执行存储器访问操作而不是分支操作的执行资源集群分配。 对另一组微操作执行资源从可执行分支操作而不是存储器访问操作的执行资源集群分配。 第一组和第二组微操作可以按顺序执行，但是退休以表示其顺序指令排序。

公开(公告)号：US20080148282A1

公开(公告)日：2008-06-19

申请号：US11641424

申请日：2006-12-18

Applicant: Avinash Sodani ,  Vijaykumar B. Kadgi ,  Zeev Sperber

Inventor： Avinash Sodani ,  Vijaykumar B. Kadgi ,  Zeev Sperber

IPC: G06F9/44

CPC classification number: G06F9/3865 ,  G06F9/3857

Abstract: Method, apparatus and system embodiments provide a register to track the oldest exception event or sticky event in a processor. The processor may be an out-of-order processor. Dispatched instructions (or micro-ops) may be maintained in a queue, such as a reorder buffer (ROB), for in-order retirement. For at least one embodiment, event information is maintained only in the register and is not maintained in a ROB. For at least one other embodiment, event information is maintained in a ROB entry for some events and in the register for others. For such latter embodiment, a retire engine takes the contents of both the ROB entry and the register into account when determining whether to take an exception or otherwise initiate a handling sequence during in-order instruction retirement. Other embodiments are also described and claimed.

Abstract translation: 方法，装置和系统实施例提供了一个寄存器来跟踪处理器中最旧的异常事件或粘性事件。 处理器可以是乱序处理器。 调度的指令（或微操作）可以被维护在队列中，例如重新排序缓冲器（ROB），用于按顺序退出。 对于至少一个实施例，事件信息仅在寄存器中被维护，并且不保持在ROB中。 对于至少一个其他实施例，事件信息在一些事件的ROB条目中以及在其他的注册中保持。 对于这样的后一个实施例，退休引擎在确定是否采取异常或在按顺序指令退出时以其他方式启动处理顺序时考虑到ROB入口和寄存器两者的内容。 还描述和要求保护其他实施例。

公开(公告)号：US20080082791A1

公开(公告)日：2008-04-03

申请号：US11540337

申请日：2006-09-29

Applicant: Srinivas Chennupaty ,  Avinash Sodani ,  Brent Boswell ,  Mark Seconi

Inventor： Srinivas Chennupaty ,  Avinash Sodani ,  Brent Boswell ,  Mark Seconi

IPC: G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/30101 ,  G06F9/3824 ,  G06F9/3838 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/462

Abstract: In one embodiment, the present invention includes a method for assigning a first identifier to a first instruction that is to write control information into a configuration register, assigning the first identifier to a second instruction that is to read the control information written by the first instruction, and storing the second instruction in a first structure of a processor with the first identifier. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种用于将第一标识符分配给第一指令的方法，该第一指令将控制信息写入配置寄存器，将第一标识符分配给第二指令，该第二指令将读取由第一指令写入的控制信息 并且将第二指令存储在具有第一标识符的处理器的第一结构中。 描述和要求保护其他实施例。

公开(公告)号：US20050091475A1

公开(公告)日：2005-04-28

申请号：US10692436

申请日：2003-10-22

Applicant: Avinash Sodani

Inventor： Avinash Sodani

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/3836 ,  G06F9/30101 ,  G06F9/30141 ,  G06F9/3808 ,  G06F9/384 ,  G06F9/3857

Abstract: A method and apparatus for a microprocessor with a divided register alias table is disclosed. In one embodiment, a first register alias table may have a full set of read and write ports, and a second register alias table may have a smaller set of read and write ports. The second register alias table may include translations for those logical register addresses that are used less frequently. When the second register alias table is called upon to translate more logical register addresses than it has read ports, in one embodiment a pipeline stall may permit additional time to utilize the limited read ports. In another embodiment, additional build rules for a trace cache may be utilized.

Abstract translation: 公开了一种具有分割寄存器别名表的微处理器的方法和装置。 在一个实施例中，第一寄存器别名表可以具有完整的读取和写入端口集合，并且第二寄存器别名表可以具有较小的读取和写入端口集合。 第二寄存器别名表可以包括那些频繁使用的逻辑寄存器地址的转换。 当第二寄存器别名表被调用以转换比读取端口更多的逻辑寄存器地址时，在一个实施例中，流水线停顿可以允许额外的时间来利用有限的读取端口。 在另一个实施例中，可以利用跟踪高速缓存的附加构建规则。

公开(公告)号：US20140195790A1

公开(公告)日：2014-07-10

申请号：US13994676

申请日：2011-12-28

Applicant: Matthew C. Merten ,  Avinash Sodani ,  Sean P. Mirkes ,  Vijaykumar B. Kadgi ,  Bambang Sutanto ,  Chia Yin Kevin Lai ,  Morris Marden ,  Alexandre J. Farcy

Inventor： Matthew C. Merten ,  Avinash Sodani ,  Sean P. Mirkes ,  Vijaykumar B. Kadgi ,  Bambang Sutanto ,  Chia Yin Kevin Lai ,  Morris Marden ,  Alexandre J. Farcy

IPC: G06F9/38

CPC classification number: G06F9/3844 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3867 ,  G06F9/3885

Abstract: A secondary jump execution unit (JEU) is incorporated in a micro-processor to operate concurrently with a primary JEU, enabling the execution of simultaneous branch operations with possible detection of multiple branch mispredicts. When branch operations are executed on both JEUs in a same instruction cycle, mispredict processing for the secondary JEU is skidded into the primary JEU's dispatch pipeline such that the branch processing for the secondary JEU occurs after processing of the branch for the primary JEU and while the primary JEU is not processing a branch. Moreover, in cases when a nuke command is also received from a reorder buffer of the processor, the branch processing for the secondary JEU is further delayed to accommodate processing of the nuke on the primary JEU. Further embodiments support the promotion of the secondary JEU to have access to the mispredict mechanisms of the primary JEU in certain circumstances.

Abstract translation: 次级跳转执行单元（JEU）并入微处理器以与主JEU同时操作，使得能够执行同时分支操作，并可能检测到多个分支错误预测。 当在同一个指令周期中对两个JEU执行分支操作时，辅助JEU的错误预测处理被划分到主JEU的调度流水线中，使得辅助JEU的分支处理在主JEU的分支处理之后发生，而 初级JEU不处理分支。 此外，在从处理器的重新排序缓冲器接收到nuke命令的情况下，进一步延迟用于辅助JEU的分支处理，以适应主JEU上的nuke的处理。 进一步的实施方案支持促进联合联合国次级方案在某些情况下获得主要联合执行机构的错误预测机制。