公开(公告)号：US07671681B2

公开(公告)日：2010-03-02

申请号：US10282688

申请日：2002-10-29

申请人： Arya R. Behzad ,  Klaas Bult ,  Ramon A. Gomez ,  Chi-Hung Lin ,  Tom W. Kwan ,  Oscar E. Agazzi ,  John L. Creigh ,  Mehdi Hatamian ,  David E. Kruse ,  Arthur Abnous ,  Henry Samueli

发明人： Arya R. Behzad ,  Klaas Bult ,  Ramon A. Gomez ,  Chi-Hung Lin ,  Tom W. Kwan ,  Oscar E. Agazzi ,  John L. Creigh ,  Mehdi Hatamian ,  David E. Kruse ,  Arthur Abnous ,  Henry Samueli

IPC分类号： H03G3/10

CPC分类号： H03F1/32 ,  H03F3/347 ,  H03F3/505 ,  H03F2200/211 ,  H03F2200/252 ,  H03F2200/421 ,  H03F2200/513 ,  H03G1/0088 ,  H03G3/001 ,  H03G3/3036 ,  H03G3/3052 ,  H03G5/10 ,  H03H11/245

摘要： Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

摘要翻译： 电路从集成电路可编程增益衰减器中的信号路径中去除开关。 可编程增益衰减器和可编程增益放大器通常使用半导体开关在信号电平之间切换。 这种开关可能在信号中引入非线性。 通过将开关与信号路径隔离，可以提高PGA的线性度。

公开(公告)号：US07466751B2

公开(公告)日：2008-12-16

申请号：US11204534

申请日：2005-08-16

申请人： Oscar E. Azazzi ,  David Kruse ,  Arthur Abnous ,  Mehdi Hatamian

发明人： Oscar E. Azazzi ,  David Kruse ,  Arthur Abnous ,  Mehdi Hatamian

IPC分类号： H03H7/30

CPC分类号： H04L7/0062 ,  G01R31/3004 ,  G01R31/3008 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/318502 ,  G01R31/318552 ,  G01R31/318594 ,  H03M13/256 ,  H03M13/41 ,  H04B3/23 ,  H04B3/32 ,  H04L1/0054 ,  H04L1/0059 ,  H04L1/242 ,  H04L7/0334 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03203 ,  H04L25/03267 ,  H04L25/03324 ,  H04L25/067 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/497 ,  H04L2025/03363 ,  H04L2025/03369 ,  H04L2025/03458 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03496 ,  H04L2025/03503 ,  H04L2025/03617 ,  H04L2025/03643 ,  H04L2025/03745

摘要： A method and a system for providing ISI compensation to an input signal in a bifurcated manner. ISI compensation is provided in two stages, a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel. First stage ISI compensation is performed in an inverse response filter having a characteristic feedback gain factor K, during system start-up. Second stage ISI compensation is performed by a single DFE in combination with a MDFE operating on tentative decisions output from a Viterbi decoder. As the DFE of the second stage reaches convergence, the feedback gain factor K of the first stage is ramped to zero.

摘要翻译： 一种用于以分叉方式向输入信号提供ISI补偿的方法和系统。 ISI补偿分两阶段提供，第一级补偿由发射机的部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由多对传输信道的特性引起的ISI分量。 在系统启动期间，在具有特性反馈增益因子K的逆响应滤波器中执行第一级ISI补偿。 第二级ISI补偿由单个DFE与由维特比解码器输出的暂定决定操作的MDFE组合执行。 当第二级的DFE达到收敛时，第一级的反馈增益因子K变为零。

公开(公告)号：US07453935B2

公开(公告)日：2008-11-18

申请号：US11688669

申请日：2007-03-20

申请人： Oscar E. Agazzi ,  John L. Creigh ,  Mehdi Hatamian ,  David E. Kruse ,  Arthur Abnous ,  Henry Samueli

发明人： Oscar E. Agazzi ,  John L. Creigh ,  Mehdi Hatamian ,  David E. Kruse ,  Arthur Abnous ,  Henry Samueli

IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC分类号： H04L7/0062 ,  G01R31/3004 ,  G01R31/3008 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/318502 ,  G01R31/318552 ,  G01R31/318594 ,  H04B3/23 ,  H04B3/235 ,  H04B3/32 ,  H04L1/0021 ,  H04L1/0047 ,  H04L1/0053 ,  H04L1/0054 ,  H04L1/0059 ,  H04L1/006 ,  H04L1/242 ,  H04L7/0334 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03197 ,  H04L25/03203 ,  H04L25/03235 ,  H04L25/03267 ,  H04L25/03987 ,  H04L25/067 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/497 ,  H04L2001/0096 ,  H04L2025/03363 ,  H04L2025/03369 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03496 ,  H04L2025/03503 ,  H04L2025/03617 ,  H04L2025/03745

摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

摘要翻译： 公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机的部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。 基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。 通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。 生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。 调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

公开(公告)号：US07305029B2

公开(公告)日：2007-12-04

申请号：US10681624

申请日：2003-10-08

申请人： Oscar E. Agazzi ,  John L. Creigh ,  Mehdi Hatamian ,  David E. Kruse ,  Arthur Abnous ,  Henry Samueli

发明人： Oscar E. Agazzi ,  John L. Creigh ,  Mehdi Hatamian ,  David E. Kruse ,  Arthur Abnous ,  Henry Samueli

IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC分类号： H04L7/0062 ,  G01R31/3004 ,  G01R31/3008 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/318502 ,  G01R31/318552 ,  G01R31/318594 ,  H04B3/23 ,  H04B3/235 ,  H04B3/32 ,  H04L1/0021 ,  H04L1/0047 ,  H04L1/0053 ,  H04L1/0054 ,  H04L1/0059 ,  H04L1/006 ,  H04L1/242 ,  H04L7/0334 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03197 ,  H04L25/03203 ,  H04L25/03235 ,  H04L25/03267 ,  H04L25/03987 ,  H04L25/067 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/497 ,  H04L2001/0096 ,  H04L2025/03363 ,  H04L2025/03369 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03496 ,  H04L2025/03503 ,  H04L2025/03617 ,  H04L2025/03745

摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

摘要翻译： 公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机的部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。 基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。 通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。 生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。 调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

公开(公告)号：US07194029B2

公开(公告)日：2007-03-20

申请号：US10681444

申请日：2003-10-08

申请人： Oscar E. Agazzi ,  John L. Creigh ,  Mehdi Hatamian ,  David E. Kruse ,  Arthur Abnous ,  Henry Samueli

发明人： Oscar E. Agazzi ,  John L. Creigh ,  Mehdi Hatamian ,  David E. Kruse ,  Arthur Abnous ,  Henry Samueli

IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC分类号： H04L7/0062 ,  G01R31/3004 ,  G01R31/3008 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/318502 ,  G01R31/318552 ,  G01R31/318594 ,  H04B3/23 ,  H04B3/235 ,  H04B3/32 ,  H04L1/0021 ,  H04L1/0047 ,  H04L1/0053 ,  H04L1/0054 ,  H04L1/0059 ,  H04L1/006 ,  H04L1/242 ,  H04L7/0334 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03197 ,  H04L25/03203 ,  H04L25/03235 ,  H04L25/03267 ,  H04L25/03987 ,  H04L25/067 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/497 ,  H04L2001/0096 ,  H04L2025/03363 ,  H04L2025/03369 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03496 ,  H04L2025/03503 ,  H04L2025/03617 ,  H04L2025/03745

摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitter's partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

摘要翻译： 公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机的部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。 基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。 通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。 生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。 调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

公开(公告)号：US07177353B2

公开(公告)日：2007-02-13

申请号：US09804082

申请日：2001-03-12

申请人： Arthur Abnous ,  Avanindra Madisetti ,  Christian A. J. Lutkemeyer

发明人： Arthur Abnous ,  Avanindra Madisetti ,  Christian A. J. Lutkemeyer

IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC分类号： H04L25/03267 ,  H04L25/03197 ,  H04L25/03235 ,  H04L25/497

摘要： A method for providing a next-cycle input sample from a decision feedback equalizer to a symbol decoder using look-ahead computations such that timing contention between the decision feedback equalizer and the symbol decoder is reduced. During a symbol period, a set of possible values is computed in the decision feedback equalizer and a set of path memory symbols is computed in the symbol decoder, the set of path memory symbols being based on a current input sample. During the same symbol period, one of the possible values is selected as the next-cycle input sample based on at least one of the next-cycle path memory symbols produced from the symbol decoder.

摘要翻译： 一种用于使用先行计算从判决反馈均衡器向符号解码器提供下一周期输入样本的方法，从而降低了判决反馈均衡器和符号解码器之间的定时争用。 在符号周期期间，在判决反馈均衡器中计算一组可能的值，并且在符号解码器中计算一组路径存储器符号，该路径存储器符号集合基于当前输入样本。 在相同的符号周期期间，基于从符号解码器产生的下一循环路径存储器符号中的至少一个，可选值中的一个被选择为下一周期输入采样。

公开(公告)号：US20060192614A1

公开(公告)日：2006-08-31

申请号：US11345946

申请日：2006-02-02

申请人： Arya Behzad ,  Klaas Bult ,  Ramon Gomez ,  Chi-Hung Lin ,  Tom Kwan ,  Oscar Agazzi ,  John Creigh ,  Mehdi Hatamian ,  David Kruse ,  Arthur Abnous ,  Henry Samueli

发明人： Arya Behzad ,  Klaas Bult ,  Ramon Gomez ,  Chi-Hung Lin ,  Tom Kwan ,  Oscar Agazzi ,  John Creigh ,  Mehdi Hatamian ,  David Kruse ,  Arthur Abnous ,  Henry Samueli

IPC分类号： H03B1/00

CPC分类号： H03F1/32 ,  H03F3/347 ,  H03F3/505 ,  H03F2200/211 ,  H03F2200/252 ,  H03F2200/421 ,  H03F2200/513 ,  H03G1/0088 ,  H03G3/001 ,  H03G3/3036 ,  H03G3/3052 ,  H03G5/10 ,  H03H11/245

摘要： Circuitry to remove switches from signal paths in integrated circuit programmable gain attenuators. Programmable gain attenuators and programmable gain amplifiers commonly switch between signal levels using semi-conductor switches. Such switches may introduce non-linearities in the signal. By isolating the switches from the signal path linearity of the PGA can be improved.

公开(公告)号：US20050036576A1

公开(公告)日：2005-02-17

申请号：US10919729

申请日：2004-08-17

申请人： Oscar Agazzi ,  John Creigh ,  Mehdi Hatamian ,  Henry Samueli ,  David Kruse ,  Arthur Abnous

发明人： Oscar Agazzi ,  John Creigh ,  Mehdi Hatamian ,  Henry Samueli ,  David Kruse ,  Arthur Abnous

IPC分类号： G01R31/30 ,  G01R31/317 ,  G01R31/3185 ,  H04B3/23 ,  H04B3/32 ,  H04L1/00 ,  H04L1/24 ,  H04L5/14 ,  H04L7/02 ,  H04L7/033 ,  H04L25/03 ,  H04L25/06 ,  H04L25/14 ,  H04L25/49 ,  H04L25/497 ,  H04L25/08

CPC分类号： H04L7/0062 ,  G01R31/3004 ,  G01R31/3008 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/318502 ,  G01R31/318552 ,  G01R31/318594 ,  H04B3/23 ,  H04B3/235 ,  H04B3/32 ,  H04L1/0021 ,  H04L1/0047 ,  H04L1/0053 ,  H04L1/0054 ,  H04L1/0059 ,  H04L1/006 ,  H04L1/242 ,  H04L7/0334 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03197 ,  H04L25/03203 ,  H04L25/03235 ,  H04L25/03267 ,  H04L25/03987 ,  H04L25/067 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/497 ,  H04L2001/0096 ,  H04L2025/03363 ,  H04L2025/03369 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03496 ,  H04L2025/03503 ,  H04L2025/03617 ,  H04L2025/03745

摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

摘要翻译： 公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。 基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。 通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。 生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。 调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

公开(公告)号：US06778602B2

公开(公告)日：2004-08-17

申请号：US10086618

申请日：2002-02-28

申请人： Oscar E. Agazzi ,  John L. Creigh ,  Mehdi Hatamian ,  Henry Samueli ,  David E. Kruse ,  Arthur Abnous

发明人： Oscar E. Agazzi ,  John L. Creigh ,  Mehdi Hatamian ,  Henry Samueli ,  David E. Kruse ,  Arthur Abnous

IPC分类号： H03H730

CPC分类号： H04L7/0062 ,  G01R31/3004 ,  G01R31/3008 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/318502 ,  G01R31/318552 ,  G01R31/318594 ,  H04B3/23 ,  H04B3/235 ,  H04B3/32 ,  H04L1/0021 ,  H04L1/0047 ,  H04L1/0053 ,  H04L1/0054 ,  H04L1/0059 ,  H04L1/006 ,  H04L1/242 ,  H04L7/0334 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03197 ,  H04L25/03203 ,  H04L25/03235 ,  H04L25/03267 ,  H04L25/03987 ,  H04L25/067 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/497 ,  H04L2001/0096 ,  H04L2025/03363 ,  H04L2025/03369 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03496 ,  H04L2025/03503 ,  H04L2025/03617 ,  H04L2025/03745

摘要： Various systems and methods providing high speed decoding, enhanced power reduction and clock domain partitioning for a multi-pair gigabit Ethernet transceiver are disclosed. ISI compensation is partitioned into two stages; a first stage compensates ISI components induced by characteristics of a transmitters partial response pulse shaping filter in a demodulator, a second stage compensates ISI components induced by characteristics of a multi-pair transmission channel in a Viterbi decoder. High speed decoding is accomplished by reducing the DFE depth by providing an input signal from a multiple decision feedback equalizer to the Viterbi based on a tail value and a subset of coefficient values received from a unit depth decision-feedback equalizer. Power reduction is accomplished by adaptively truncating active taps in the NEXT, FEXT and echo cancellation filters, or by disabling decoder circuitry portions, as channel response characteristics allow. A receive clock signal is generated such that it is synchronous in frequency with analog sampling clock signals and has a particular phase offset with respect to one of the sampling clock signals. This phase offset is adjusted such that system performance degradation due to coupling of switching noise from the digital sections to the analog sections is substantially minimized.

摘要翻译： 公开了为多对千兆位以太网收发器提供高速解码，增强的功率降低和时钟域划分的各种系统和方法。 ISI补偿分为两个阶段; 第一级补偿由解调器中的发射机部分响应脉冲整形滤波器的特性引起的ISI分量，第二级补偿由维特比解码器中的多对传输信道的特性引起的ISI分量。 基于从单位深度判决反馈均衡器接收的尾值和系数值的子集，通过从多个判决反馈均衡器向维特比提供输入信号来减小DFE深度来实现高速解码。 通过自适应地截断NEXT，FEXT和回声消除滤波器中的有源抽头，或通过禁用解码器电路部分，如通道响应特性允许，实现功率降低。 生成接收时钟信号，使得其与模拟采样时钟信号在频率上同步，并且相对于采样时钟信号之一具有特定的相位偏移。 调整该相位偏移，使得由于来自数字部分到模拟部分的开关噪声的耦合而导致的系统性能降低被大大减小。

公开(公告)号：US06721916B2

公开(公告)日：2004-04-13

申请号：US09858990

申请日：2001-05-15

申请人： Oscar E. Agazzi ,  David Kruse ,  Arthur Abnous ,  Mehdi Hatamian

发明人： Oscar E. Agazzi ,  David Kruse ,  Arthur Abnous ,  Mehdi Hatamian

IPC分类号： H03M1303

CPC分类号： H04L7/0062 ,  G01R31/3004 ,  G01R31/3008 ,  G01R31/3016 ,  G01R31/31715 ,  G01R31/318502 ,  G01R31/318552 ,  G01R31/318594 ,  H04B3/23 ,  H04B3/32 ,  H04L1/0054 ,  H04L1/0059 ,  H04L1/242 ,  H04L7/0334 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03146 ,  H04L25/03267 ,  H04L25/067 ,  H04L25/14 ,  H04L25/4917 ,  H04L25/497 ,  H04L2025/03363 ,  H04L2025/03369 ,  H04L2025/03477 ,  H04L2025/0349 ,  H04L2025/03496 ,  H04L2025/03503 ,  H04L2025/03617 ,  H04L2025/03745

摘要： A method and a system for decoding information signals encoded in accordance with a multi-state encoding scheme and transmitted over a multi-dimensional transmission channel by computing a distance of a received word from a codeword. One-dimensional (1D) input signals are processed in a pair of symbol decoders, implemented as look-up tables, to produce a pair of 1D errors, with each representing a distance metric between the input signal and a symbol in a set of symbols. The 1D errors are combined based on the multi-state encoding scheme in order to produce a set of multi-dimensional error terms. Each of the multi-dimensional error terms corresponds to a distance between a received word and a nearest codeword.

摘要翻译： 一种用于对根据多状态编码方案编码并通过计算从码字的接收字的距离而在多维传输信道上传送的信息信号的方法和系统。 一维（1D）输入信号在一对符号解码器中被处理，被实现为查找表，以产生一对1D误差，每一个代表一个输入信号和一组符号中的符号之间的距离度量 。 基于多状态编码方案组合1D误差，以产生一组多维误差项。 多维误差项中的每一个对应于接收到的字和最近的码字之间的距离。