公开(公告)号：US20140181464A1

公开(公告)日：2014-06-26

申请号：US13997784

申请日：2012-12-26

Applicant: Andrew T. Forsyth ,  Brian J. Hickmann ,  Jonathan C. Hall ,  Christopher J. Hughes

Inventor： Andrew T. Forsyth ,  Brian J. Hickmann ,  Jonathan C. Hall ,  Christopher J. Hughes

IPC: G06F12/10

CPC classification number: G06F9/3853 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30098 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3804 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3887 ,  G06F12/0875 ,  G06F12/1027 ,  G06F13/4282 ,  G06F15/8007 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/68

Abstract: According to one embodiment, a processor includes an instruction decoder to decode a first instruction to gather data elements from memory, the first instruction having a first operand specifying a first storage location and a second operand specifying a first memory address storing a plurality of data elements. The processor further includes an execution unit coupled to the instruction decoder, in response to the first instruction, to read contiguous a first and a second of the data elements from a memory location based on the first memory address indicated by the second operand, and to store the first data element in a first entry of the first storage location and a second data element in a second entry of a second storage location corresponding to the first entry of the first storage location.

Abstract translation: 根据一个实施例，处理器包括指令解码器，用于解码从存储器收集数据元素的第一指令，所述第一指令具有指定第一存储位置的第一操作数和指定存储多个数据元素的第一存储器地址的第二操作数 。 处理器还包括执行单元，其响应于第一指令而耦合到指令解码器，基于由第二操作数指示的第一存储器地址从存储器位置读取连续的第一和第二数据元素，并且 将所述第一数据元素存储在所述第一存储位置的第一条目中，以及将第二数据元素存储在与所述第一存储位置的所述第一条目相对应的第二存储位置的第二条目中。

公开(公告)号：US20140095831A1

公开(公告)日：2014-04-03

申请号：US13631071

申请日：2012-09-28

Applicant: Edward T. Grochowski ,  Dennis R. Bradford ,  George Z. Chrysos ,  Andrew T. Forsyth ,  Michael D. Upton ,  Lisa K. Wu

Inventor： Edward T. Grochowski ,  Dennis R. Bradford ,  George Z. Chrysos ,  Andrew T. Forsyth ,  Michael D. Upton ,  Lisa K. Wu

IPC: G06F9/30

CPC classification number: G06F9/30036 ,  G06F9/30018 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/345 ,  G06F9/355

Abstract: An apparatus and method are described for performing efficient gather operations in a pipelined processor. For example, a processor according to one embodiment of the invention comprises: gather setup logic to execute one or more gather setup operations in anticipation of one or more gather operations, the gather setup operations to determine one or more addresses of vector data elements to be gathered by the gather operations; and gather logic to execute the one or more gather operations to gather the vector data elements using the one or more addresses determined by the gather setup operations.

Abstract translation: 描述了一种用于在流水线处理器中执行有效收集操作的装置和方法。 例如，根据本发明的一个实施例的处理器包括：收集设置逻辑，用于在预期一个或多个收集操作中执行一个或多个收集设置操作，所述收集设置操作确定向量数据元素的一个或多个地址 聚集在一起聚集; 并收集逻辑以执行一个或多个收集操作以使用由收集设置操作确定的一个或多个地址来收集向量数据元素。

公开(公告)号：US20140052969A1

公开(公告)日：2014-02-20

申请号：US13976997

申请日：2011-12-23

Applicant: Jesus Corbal ,  Andrew T. Forsyth ,  Thomas D. Fletcher ,  Lisa K. Wu ,  Eric Sprangle

Inventor： Jesus Corbal ,  Andrew T. Forsyth ,  Thomas D. Fletcher ,  Lisa K. Wu ,  Eric Sprangle

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30145 ,  G06F9/3893

Abstract: A processing core is described having execution unit logic circuitry having a first register to store a first vector input operand, a second register to a store a second vector input operand and a third register to store a packed data structure containing scalar input operands a, b, c. The execution unit logic circuitry further include a multiplier to perform the operation (a*(first vector input operand))+(b*(second vector operand))+c.

Abstract translation: 描述处理核心，其具有执行单元逻辑电路，其具有第一寄存器以存储第一向量输入操作数，第二寄存器存储第二向量输入操作数和第三寄存器以存储包含标量输入操作数a，b的打包数据结构 ， C。 执行单元逻辑电路还包括执行操作的乘法器（a *（第一向量输入操作数））+（b *（第二向量操作数））+ c。

公开(公告)号：US20120079244A1

公开(公告)日：2012-03-29

申请号：US12890571

申请日：2010-09-24

Applicant: Andrew T. Forsyth

Inventor： Andrew T. Forsyth

IPC: G06F9/305

CPC classification number: G06F9/30167 ,  G06F9/30029 ,  G06F9/30036 ,  G06F9/34

Abstract: An apparatus and method are described for performing arbitrary logical operations specified by a table. For example, one embodiment of a method for performing a logical operation on a computer processor comprises: reading data from each of two or more source operands; combining the data read from the source operands to generate an index value, the index value identifying a subset of bits within an immediate value transmitted with an instruction; reading the bits from the immediate value; and storing the bits read from the immediate value within a destination register to generate a result of the instruction.

Abstract translation: 描述了用于执行由表指定的任意逻辑操作的装置和方法。 例如，用于在计算机处理器上执行逻辑操作的方法的一个实施例包括：从两个或更多个源操作数中的每一个读取数据; 组合从源操作数读取的数据以生成索引值，所述索引值标识用指令发送的立即值内的位的子集; 从立即值读取位; 以及将从立即值读取的比特存储在目的地寄存器中，以生成该指令的结果。

公开(公告)号：US20110153989A1

公开(公告)日：2011-06-23

申请号：US12644529

申请日：2009-12-22

Applicant: Ravi Rajwar ,  Andrew T. Forsyth

Inventor： Ravi Rajwar ,  Andrew T. Forsyth

IPC: G06F9/30 ,  G06F9/312

CPC classification number: G06F9/30021 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30087

Abstract: A vector compare-and-exchange operation is performed by: decoding by a decoder in a processing device, a single instruction specifying a vector compare-and-exchange operation for a plurality of data elements between a first storage location, a second storage location, and a third storage location; issuing the single instruction for execution by an execution unit in the processing device; and responsive to the execution of the single instruction, comparing data elements from the first storage location to corresponding data elements in the second storage location; and responsive to determining a match exists, replacing the data elements from the first storage location with corresponding data elements from the third storage location.

Abstract translation: 通过以下操作来执行向量比较和交换操作：通过处理设备中的解码器进行解码，指定在第一存储位置，第二存储位置和第二存储位置之间的多个数据元素的向量比较和交换操作的单个指令， 和第三存储位置; 发出由处理装置中的执行单元执行的单个指令; 并且响应于所述单个指令的执行，将来自所述第一存储位置的数据元素与所述第二存储位置中的相应数据元素进行比较; 并且响应于确定匹配存在，用来自第三存储位置的相应数据元素从第一存储位置替换数据元素。

公开(公告)号：US09766886B2

公开(公告)日：2017-09-19

申请号：US13977736

申请日：2011-12-16

Applicant: Jesus Corbal ,  Andrew T. Forsyth ,  Lisa K. Wu ,  Thomas D. Fletcher

Inventor： Jesus Corbal ,  Andrew T. Forsyth ,  Lisa K. Wu ,  Thomas D. Fletcher

IPC: G06F9/302 ,  G06F9/315 ,  G06F17/17 ,  G09G5/00 ,  G06F15/76 ,  G06F9/30 ,  G06F9/38 ,  G06T3/40 ,  G06F15/80

CPC classification number: G06F9/30036 ,  G06F9/30007 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30185 ,  G06F9/3836 ,  G06F15/8053 ,  G06F17/17 ,  G06T3/4007

Abstract: Instructions and logic provide vector linear interpolation functionality. In some embodiments, responsive to an instruction specifying: a first operand from a set of vector registers, a size of each of the vector elements, a portion of the vector elements upon which to compute linear interpolations, a second operand from a set of vector registers, and a third operand; an execution unit, reads a first, a second and a third value of the size of vector elements from corresponding data fields in the first, the second and the third operand respectively and computes an interpolated value as the first value multiplied by the second value minus the second value multiplied by the third value plus the third value.

公开(公告)号：US09733935B2

公开(公告)日：2017-08-15

申请号：US13976404

申请日：2011-12-23

Applicant: Jesus Corbal ,  Andrew T. Forsyth ,  Roger Espasa ,  Manel Fernandez ,  Thomas D. Fletcher

Inventor： Jesus Corbal ,  Andrew T. Forsyth ,  Roger Espasa ,  Manel Fernandez ,  Thomas D. Fletcher

IPC: G06F9/30

CPC classification number: G06F9/3001 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30101 ,  G06F9/30145

Abstract: A method of processing an instruction is described that includes fetching and decoding the instruction. The instruction has separate destination address, first operand source address and second operand source address components. The first operand source address identifies a location of a first mask pattern in mask register space. The second operand source address identifies a location of a second mask pattern in the mask register space. The method further includes fetching the first mask pattern from the mask register space; fetching the second mask pattern from the mask register space; merging the first and second mask patterns into a merged mask pattern; and, storing the merged mask pattern at a storage location identified by the destination address.

公开(公告)号：US20160041827A1

公开(公告)日：2016-02-11

申请号：US13995944

申请日：2011-12-23

Applicant: Jesus Corbal ,  Matthew J Craighead ,  Dennis R Bradford ,  Jonathan C. Hall ,  Andrew T. Forsyth

Inventor： Jesus Corbal ,  Matthew J Craighead ,  Dennis R Bradford ,  Jonathan C. Hall ,  Andrew T. Forsyth

IPC: G06F9/30

CPC classification number: G06F9/30018 ,  G06F9/30032 ,  G06F9/30036

Abstract: A method is described that includes fetching an instruction and decoding the instruction. The method further includes fetching a first mask vector from a first mask register space location identified by the instruction. The method further includes fetching a second mask vector from a second mask register space location identified by the instruction. The method also includes executing the instruction by merging the first and second mask vectors into a single data structure and causing the single data structure to be written into a memory location identified by the instruction.

Abstract translation: 描述了一种包括获取指令并解码指令的方法。 该方法还包括从由该指令识别的第一屏蔽寄存器空间位置获取第一屏蔽矢量。 该方法还包括从由该指令识别的第二屏蔽寄存器空间位置获取第二屏蔽矢量。 该方法还包括通过将第一和第二屏蔽矢量合并为单个数据结构并使单个数据结构被写入由该指令识别的存储器位置来执行该指令。

公开(公告)号：US20110148894A1

公开(公告)日：2011-06-23

申请号：US12642917

申请日：2009-12-21

Applicant: Jean-Luc Duprat ,  Paul Lalonde ,  Andrew T. Forsyth

Inventor： Jean-Luc Duprat ,  Paul Lalonde ,  Andrew T. Forsyth

IPC: G06T11/40

CPC classification number: G06T11/001 ,  G06T9/00 ,  G06T15/04 ,  H04N19/60

Abstract: A method and system may include a chip having graphics rendering hardware, a cache and a processor to execute an application with texture allocation logic to receive notification of a page miss from the graphics rendering hardware. The logic can map the page miss to a tile of a texture image, store the tile as an entry to the cache, and map the entry to a virtual address space of a virtual image corresponding to the texture image. The system may also include off-chip memory to store the texture image.

Abstract translation: 方法和系统可以包括具有图形绘制硬件的芯片，高速缓存和处理器，以执行具有纹理分配逻辑的应用，以从图形呈现硬件接收页面未命中的通知。 逻辑可以将页面未命中映射到纹理图像的瓦片，将瓦片作为条目存储到高速缓存，并将条目映射到与纹理图像相对应的虚拟图像的虚拟地址空间。 该系统还可以包括用于存储纹理图像的片外存储器。