公开(公告)号：US20140229721A1

公开(公告)日：2014-08-14

申请号：US13997828

申请日：2012-03-30

Applicant: Andrew T. Forsyth ,  Renju Thomas ,  Jean-Luc Duprat

Inventor： Andrew T. Forsyth ,  Renju Thomas ,  Jean-Luc Duprat

IPC: G06F9/38

CPC classification number: G06F9/3806 ,  G06F9/3005 ,  G06F9/3844 ,  G06F9/3846 ,  G06F9/3848

Abstract: A processor includes an execution pipeline having one or more execution units to execution the instructions and a branch prediction unit coupled to the execution units. The branch prediction unit includes a branch history table to store prior branch predictions, a branch predictor, in response to a conditional branch instruction, to predict a branch target address of the conditional branch instruction based on the branch history table, and address match logic to compare the predicted branch target address with an address of a next instruction executed immediately following the conditional branch instruction. The address match logic is to cause the execution pipeline to be flushed if the predicted branch target address does not match the address of the next instruction to be executed.

Abstract translation: 处理器包括具有执行指令的一个或多个执行单元的执行流水线和耦合到执行单元的分支预测单元。 分支预测单元包括用于存储先前分支预测的分支历史表，分支预测器，响应于条件分支指令，基于分支历史表预测条件分支指令的分支目标地址，以及地址匹配逻辑 将预测分支目标地址与紧随条件分支指令之后执行的下一条指令的地址进行比较。 如果预测的分支目标地址与要执行的下一条指令的地址不匹配，地址匹配逻辑将使执行流水线被刷新。

公开(公告)号：US09851973B2

公开(公告)日：2017-12-26

申请号：US13997828

申请日：2012-03-30

Applicant: Andrew T. Forsyth ,  Renju Thomas ,  Jean-Luc Duprat

Inventor： Andrew T. Forsyth ,  Renju Thomas ,  Jean-Luc Duprat

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3806 ,  G06F9/3005 ,  G06F9/3844 ,  G06F9/3846 ,  G06F9/3848

Abstract: A processor includes an execution pipeline having one or more execution units to execute instructions and a branch prediction unit coupled to the execution units. The branch prediction unit includes a branch history table to store prior branch predictions, a branch predictor, in response to a conditional branch instruction, to predict a branch target address of the conditional branch instruction based on the branch history table, and address match logic to compare the predicted branch target address with an address of a next instruction executed immediately following the conditional branch instruction. The address match logic is to cause the execution pipeline to be flushed if the predicted branch target address does not match the address of the next instruction to be executed.

公开(公告)号：US09024959B2

公开(公告)日：2015-05-05

申请号：US12642917

申请日：2009-12-21

Applicant: Jean-Luc Duprat ,  Paul Lalonde ,  Andrew T Forsyth

Inventor： Jean-Luc Duprat ,  Paul Lalonde ,  Andrew T Forsyth

IPC: G06T11/40 ,  G09G5/00 ,  G06T17/00 ,  G06T11/00 ,  G06T15/04

CPC classification number: G06T11/001 ,  G06T9/00 ,  G06T15/04 ,  H04N19/60

Abstract: A method and system may include a chip having graphics rendering hardware, a cache and a processor to execute an application with texture allocation logic to receive notification of a page miss from the graphics rendering hardware. The logic can map the page miss to a tile of a texture image, store the tile as an entry to the cache, and map the entry to a virtual address space of a virtual image corresponding to the texture image. The system may also include off-chip memory to store the texture image.

Abstract translation: 方法和系统可以包括具有图形绘制硬件的芯片，高速缓存和处理器，以执行具有纹理分配逻辑的应用，以从图形呈现硬件接收页面未命中的通知。 逻辑可以将页面未命中映射到纹理图像的瓦片，将瓦片作为条目存储到高速缓存，并将条目映射到与纹理图像相对应的虚拟图像的虚拟地址空间。 该系统还可以包括用于存储纹理图像的片外存储器。

公开(公告)号：US20110148894A1

公开(公告)日：2011-06-23

申请号：US12642917

申请日：2009-12-21

Applicant: Jean-Luc Duprat ,  Paul Lalonde ,  Andrew T. Forsyth

Inventor： Jean-Luc Duprat ,  Paul Lalonde ,  Andrew T. Forsyth

IPC: G06T11/40

CPC classification number: G06T11/001 ,  G06T9/00 ,  G06T15/04 ,  H04N19/60

Abstract: A method and system may include a chip having graphics rendering hardware, a cache and a processor to execute an application with texture allocation logic to receive notification of a page miss from the graphics rendering hardware. The logic can map the page miss to a tile of a texture image, store the tile as an entry to the cache, and map the entry to a virtual address space of a virtual image corresponding to the texture image. The system may also include off-chip memory to store the texture image.

Abstract translation: 方法和系统可以包括具有图形绘制硬件的芯片，高速缓存和处理器，以执行具有纹理分配逻辑的应用，以从图形呈现硬件接收页面未命中的通知。 逻辑可以将页面未命中映射到纹理图像的瓦片，将瓦片作为条目存储到高速缓存，并将条目映射到与纹理图像相对应的虚拟图像的虚拟地址空间。 该系统还可以包括用于存储纹理图像的片外存储器。