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21.发明授权Data slicer for demodulated binary FSK signals in a time division duplex radio environment 失效用于时分双工无线电环境中解调的二进制FSK信号的数据限幅器
公开(公告)号：US5933455A
公开(公告)日：1999-08-03
申请号：US864651
申请日：1997-05-28
申请人： Alan F. Hendrickson , Peter Sheldon
发明人： Alan F. Hendrickson , Peter Sheldon
CPC分类号： H04L25/062 , H04L27/142
摘要： Method and apparatus for providing a FSK data slicer for use in wireless telecommunications such as cordless telephones. The FSK data slicer is used by a receiver circuit in a wireless telecommunication device for converting an analog data signal to a digital data signal. Furthermore, the FSK data slicer responds to different mode of the analog data signal. The FSK data slicer includes a low-pass filter, a controller, a comparator, and an integrator. The low-pass filter receives the analog data signal for generating a median voltage, or slice voltage. Furthermore, the low-pass filter includes connectors to allow an external resistor to be serially connected between the filter input and the analog data signal and to allow an external capacitor to be connected in parallel with the slice voltage at the filter output. The bandwidth of the low-pass filter is controlled by the controller. The controller responds to specific intervals of the TDD frames, initial acquisition of data in the analog data signal, and known characteristics of the TDD frames and adjusts the low-pass filter bandwidth, accordingly. As a result, the low-pass filter drives the slice voltage only when it can do so accurately, and drives it strongly when the slice voltage will be very accurate. The comparator receives and compares the analog data signal and the slice voltage in order to produce a digital data signal. The digital data signal is then sent to the integrator, which over-samples each data bit of the digital data signal. The over-sampling is concentrated on the middle three quarters of each data bit, thereby ensuring the highest level of reliability.
摘要翻译： 用于提供无线电话中使用的FSK数据限幅器的方法和装置，例如无绳电话。 FSK数据限幅器由无线电信设备中的接收机电路使用，用于将模拟数据信号转换为数字数据信号。 此外，FSK数据限幅器响应模拟数据信号的不同模式。 FSK数据限幅器包括一个低通滤波器，一个控制器，一个比较器和一个积分器。 低通滤波器接收用于产生中间电压或切片电压的模拟数据信号。 此外，低通滤波器包括连接器，以允许外部电阻器串联连接在滤波器输入端和模拟数据信号之间，并允许外部电容器与滤波器输出端的限幅电压并联连接。 低通滤波器的带宽由控制器控制。 控制器响应于TDD帧的特定间隔，模拟数据信号中数据的初始采集以及TDD帧的已知特性，并相应地调整低通滤波器带宽。 因此，低通滤波器只有在精确地进行切割电压时才能驱动分片电压，并且当切片电压非常精确时会驱动它。 比较器接收并比较模拟数据信号和限幅电压，以产生数字数据信号。 然后将数字数据信号发送到积分器，积分器对数字数据信号的每个数据位进行过采样。 过采样集中在每个数据位的中间四分之三，从而确保最高的可靠性。
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22.发明授权Dual-mode baseband controller for radio-frequency interfaces relating to digital cordless telephones 失效用于与数字无绳电话有关的射频接口的双模式基带控制器
公开(公告)号：US5638405A
公开(公告)日：1997-06-10
申请号：US192046
申请日：1994-02-04
CPC分类号： H04L27/12 , H04L27/2017 , H04M1/72502
摘要： A dual-mode baseband controller enables a single integrated circuit to support either In-Phase Quadrature (I-Q) or Non-Return to Zero (NRZ) radio-frequency transmitter architectures for use in second generation (CT2) cordless telephones. A radio frequency (RF) interface circuit controls output signals to support either the I-Q architecture or the NRZ architecture, depending on a MODE control bit received from a controlling integrated circuit. The RF interface circuit comprises an I-Q waveform generator, four multiplexers, two digital-to-analog converters, a buffer, interconnecting circuitry, and a timing controller operating under configurable software control.
摘要翻译： 双模式基带控制器使单个集成电路能够支持用于第二代（CT2）无绳电话的同相正交（I-Q）或非归零（NRZ）射频发射机架构。 根据从控制集成电路接收的MODE控制位，射频（RF）接口电路控制输出信号以支持I-Q架构或NRZ架构。 RF接口电路包括I-Q波形发生器，四个多路复用器，两个数模转换器，缓冲器，互连电路和在可配置的软件控制下操作的定时控制器。
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23.发明授权Method and apparatus for protecting cordless telephone account authentication information 失效用于保护无绳电话帐户认证信息的方法和装置
公开(公告)号：US5384847A
公开(公告)日：1995-01-24
申请号：US130636
申请日：1993-10-01
申请人： Alan F. Hendrickson , Bruno Damien
发明人： Alan F. Hendrickson , Bruno Damien
CPC分类号： H04L9/3226 , G07F7/1016 , H04L9/0894 , H04L2209/12 , H04L2209/56 , H04L2209/80
摘要： The present invention provides an apparatus for use in a telecommunication system which includes a local unit such as a cordless telephone handset and a remote unit. The apparatus generates an encrypted confirmation in the local unit in response to an inquiry received from the remote unit. The apparatus comprises receiving means for receiving the inquiry; memory means for storing a scrambled encryption key; descrambling means operatively coupled with the memory means for receiving the scrambled encryption key and for descrambling the scrambled encryption key responsive to a first predetermined digital code to produce a descrambled encryption key; and encryption means for generating an encrypted confirmation in response to the inquiry, the encrypted confirmation being encrypted using the descrambled encryption key. The invention further includes a code means such as a fuse bank for establishing the first predetermined digital code.
摘要翻译： 本发明提供一种在电信系统中使用的装置，其包括本地单元，例如无绳电话听筒和远程单元。 该装置响应于从远程单元接收到的查询，在本地单元中产生加密确认。 该装置包括用于接收查询的接收装置; 用于存储加密加密密钥的存储装置; 解扰装置与存储装置可操作地耦合，用于接收加扰的加密密钥，并响应于第一预定的数字码解密加扰的加密密钥以产生解扰的加密密钥; 以及加密装置，用于响应于所述查询产生加密确认，所述加密确认使用解扰加密密钥进行加密。 本发明还包括用于建立第一预定数字代码的代码装置，例如保险丝库。
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公开(公告)号：US5075687A
公开(公告)日：1991-12-24
申请号：US589330
申请日：1990-09-27
CPC分类号： H04M9/085
摘要： An apparatus for effecting echo suppression facilitating communications between an analog device and a digital device comprising a transmit circuit for processing outgoing signals, a receive circuit for processing incoming signals, and a control circuit for controlling the transmit circuit and the receive circuit. The transmit circuit includes transmit attenuators for attenuating the outgoing signals as they pass through the transmit circuit, and an analog-to-digital conversion circuit for converting analog signals to digital signals. The receive circuit includes receive attenuators for attenuating the incoming signals as they pass through the receive circuit and a digital-to-analog conversion circuit for converting digital signals to analog signals. Each of the transmit attenuators and the receive attenuators is digitally adjustable by the control circuit. The control circuit receives sensed outgoing signals from the transmit circuit and sensed incoming signals from the receive circuit and effects a comparison of the sensed outgoing and incoming signals to determine whether the apparatus is transmitting or receiving. The control circuit digitally adjusts the transmit attenuators and the receive attenuators to distribute a predetermined maximum loss among incoming signals and outgoing signals appropriately to increase signal attenuation in the receive circuit and reduce signal attenuation in the transmit circuit when the apparatus is transmitting, and to increase signal attenuation in the transmit circuit and decrease signal attenuation in the receive circuit when the apparatus is receiving.
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公开(公告)号：US5021783A
公开(公告)日：1991-06-04
申请号：US589402
申请日：1990-09-27
摘要： A method for operating an apparatus for facilitating communications between an analog device and a digital device, which apparatus includes a plurality of signal processing circuits and a control circuit for controlling the signal processing circuits. Each of the signal processing circuits includes signal attenuators and signal burst discrimination circuitry. The apparatus is operable in a plurality of stable states, preferably in an idle stable state, a transmit stable state, and a receive stable state. The apparatus also is operable in a plurality of transitional states, including up-transition states and down-transition states. The method includes the steps of evaluating each of the signal processing circuits by the signal burst discrimination circuitry, responding to detection of a burst indicator by setting a state indicator to an appropriate up-transition state, incrementally adjusting the attenuators in the signal processing circuits to enhance performance of the apparatus until the attenuators are at predetermined settings, periodically checking for presence of the burst indicator, on detection of cessation of the burst indicator, setting the state indicator to an appropriate down-transition state, incrementally adjusting the attenuators to redistribute attenuation losses among the signal processing circuits, if no burst indicator is detected, continuing such redistribution until the apparatus returns to the idle stable state.
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公开(公告)号：US20110235758A1
公开(公告)日：2011-09-29
申请号：US12790405
申请日：2010-05-28
申请人： Ramin Khoini-Poorfard , Alan F. Hendrickson , Alessandro Piovaccari , David S. Trager , Aslamali A. Rafi , Abdulkerim L. Coban , David Le Goff
发明人： Ramin Khoini-Poorfard , Alan F. Hendrickson , Alessandro Piovaccari , David S. Trager , Aslamali A. Rafi , Abdulkerim L. Coban , David Le Goff
CPC分类号： H04N5/455 , H03G3/001 , H03G3/002 , H03G3/3068 , H04L27/0002 , H04L27/02 , H04L27/08 , H04N5/04 , H04N5/52
摘要： A receiver circuit includes an analog front-end and a digital processing unit. The analog front-end includes an input for receiving a radio frequency (RF) signal, a first control input for receiving a gain adjustment signal, a second control input for receiving a timing signal, and a signal output for providing a digital intermediate frequency (IF) signal. The analog front-end updates gains of a plurality of gain stages according to the gain adjustment signal and in synchronism with the timing signal. The digital processing unit is configured to produce at least one output signal derived from the digital IF signal. The digital processing unit includes a timing recovery circuit configured to generate the timing signal based on the digital IF signal to control timing of the updating gains of each of the plurality of adjustable gain stages.
摘要翻译： 接收机电路包括模拟前端和数字处理单元。 模拟前端包括用于接收射频（RF）信号的输入，用于接收增益调整信号的第一控制输入，用于接收定时信号的第二控制输入和用于提供数字中频的信号输出（ IF）信号。 模拟前端根据增益调整信号更新多个增益级的增益并与定时信号同步。 数字处理单元被配置为产生从数字IF信号导出的至少一个输出信号。 数字处理单元包括定时恢复电路，其被配置为基于数字IF信号生成定时信号，以控制多个可调增益级中的每一个的更新增益的定时。
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公开(公告)号：US07577413B2
公开(公告)日：2009-08-18
申请号：US11523440
申请日：2006-09-19
CPC分类号： H04B17/21
摘要： According to a disclosed method, a calibration signal is provided at a first frequency corresponding to a low frequency edge of a desired passband to an input of a filter (240). A first value is measured at an output of the filter (240). The calibration signal is provided at a second frequency corresponding to a high frequency edge of the desired passband to the input of the filter (240). A second value is measured at the output of the filter (240). The first value is compared to the second value. A characteristic of the filter (240) is changed in response to the comparing. In one form, the filter is an IF filter (240) and a receiver (200) includes both the IF filter (240) and a calibration circuit (250) for forming the calibration signal and providing the calibration signal to the IF filter to change the characteristic in response to a calibration operation.
摘要翻译： 根据所公开的方法，将校准信号以对应于期望通带的低频边缘的第一频率提供给滤波器（240）的输入。 在过滤器（240）的输出端处测量第一值。 校准信号以对应于期望通带的高频边缘的第二频率提供给滤波器（240）的输入。 在过滤器（240）的输出处测量第二值。 将第一个值与第二个值进行比较。 响应于比较而改变过滤器（240）的特性。 在一种形式中，滤波器是IF滤波器（240），并且接收器（200）包括用于形成校准信号的IF滤波器（240）和校准电路（250），并将校准信号提供给IF滤波器以改变 响应于校准操作的特性。
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公开(公告)号：US20080111584A1
公开(公告)日：2008-05-15
申请号：US11586425
申请日：2006-10-23
IPC分类号： H03K19/0175
CPC分类号： H04M3/005
摘要： A method of calibrating longitudinal balance for a subscriber line interface circuit includes providing a first and a second driver of a differential driver pair for driving a subscriber line. An output of each of the first and second drivers is coupled to a common output. The common output is coupled to an input of the first driver. The gain of at least one of the first and second drivers is adjusted until a calibration signal (V1) present at the input of the first driver is substantially the same as a calibration signal (V2) present at the input of the second driver.
摘要翻译： 校准用户线接口电路的纵向平衡的方法包括提供用于驱动用户线的差分驱动器对的第一和第二驱动器。 第一和第二驱动器中的每一个的输出耦合到公共输出端。 公共输出耦合到第一驱动器的输入端。 调整第一和第二驱动器中的至少一个驱动器的增益，直到存在于第一驱动器的输入处的校准信号（V 1）与存在于第二驱动器的输入端的校准信号（V 2）基本相同 。
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29.发明授权Slow tracking of PN synchronization in a direct-sequence spread-spectrum digital communications system 有权在直接序列扩频数字通信系统中缓慢跟踪PN同步公开(公告)号：US06256335B1
公开(公告)日：2001-07-03
申请号：US09148269
申请日：1998-09-04
申请人： Alan F. Hendrickson
发明人： Alan F. Hendrickson
IPC分类号： H04L2730
CPC分类号： H04L1/24 , H04L7/0054 , H04L7/0334
摘要： In a direct sequence spread spectrum communication receiver, a system and method for recovering the timing of a pseudo-random noise (PN) sequence used for despreading the received signals. In one embodiment, the receiver performs a slow tracking to maintain the synchronization of the receiver's PN sequence with the received PN sequence. The slow tracking preferably includes one or more advancements or delays of the receiver's PN sequence if correlation measurements consistently indicate that the receiver's PN sequence lags or leads the received PN sequence. The slow tracking preferably also includes a long-term adjustment of the receiver's PN phase, distributed over a number of received frames, to compensate for any frequency offsets between the receiver's PN sequence and the received PN sequence. One embodiment of a system for performing the synchronization with the fast tracking includes an input for receiving a received spread-spectrum data stream, a receiver PN clock, and a slow-tracking logic. The slow-tracking logic temporarily advances and delays the receiver PN clock by a small shift and checks if either advancing or delaying consistently results in improved correlations. If so, the slow-tracking logic adjusts the receiver PN clock accordingly. The slow tracking logic preferably also includes a counter that maintains an integrated total of the adjustments to the receiver clock. The integrated total adjustment is used to determine the long-term adjustment.
摘要翻译： 在直接序列扩频通信接收机中，用于恢复用于解扩接收信号的伪随机噪声（PN）序列的定时的系统和方法。 在一个实施例中，接收机执行慢速跟踪以维持接收机的PN序列与所接收的PN序列的同步。 如果相关测量一致地指示接收机的PN序列滞后或引导接收到的PN序列，则慢跟踪优选地包括接收机的PN序列的一个或多个进步或延迟。 慢跟踪优选地还包括分布在多个接收帧上的接收机的PN相的长期调整，以补偿接收机的PN序列与接收的PN序列之间的任何频率偏移。 用于执行与快速跟踪同步的系统的一个实施例包括用于接收接收的扩频数据流，接收机PN时钟和慢跟踪逻辑的输入。 缓慢跟踪逻辑暂时推进并延迟接收器PN时钟一小段移位，并检查前进或延迟是否一致导致改进的相关性。 如果是这样，慢跟踪逻辑相应地调整接收器PN时钟。 缓慢跟踪逻辑优选地还包括保持对接收器时钟的调整的综合总计数的计数器。 综合整体调整用于确定长期调整。
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公开(公告)号：US06097768A
公开(公告)日：2000-08-01
申请号：US968202
申请日：1997-11-12
IPC分类号： G06F11/00 , H03L7/093 , H03L7/099 , H03L7/107 , H03L7/14 , H03M13/00 , H04B1/707 , H04L1/24 , H04L7/033 , H04L27/00 , H04L27/22 , H04L27/227 , H03D3/22
CPC分类号： H04L27/2275 , H03L7/0991 , H03L7/107 , H03L7/146 , H04B1/707 , H04L1/24 , H04L27/22 , H04L27/2273 , H04L27/2277 , H03L7/093 , H04L2027/0028 , H04L2027/0046 , H04L2027/0067 , H04L2027/0069 , H04L7/0334
摘要： A phase detector using simple arithmetic operations to measure phase errors in the carrier-recovery mechanism for a DQPSK digital communications receiver. The carrier-recovery mechanism is a feedback loop that provides a synchronization between the oscillators in the transmitter and receiver of the communications system; the phase detector measures deviations from this synchronization and generates a phase-error signal used in the feedback loop to synchronize the oscillators. To perform this measurement, the phase detector takes the received signal as input and compares it against a local oscillator in the receiver to generate two digital signals: the in-phase (I) and quadrature-phase (Q) components of the received signal. These signals are the input to a logic unit, which uses these two signals to determine the phase-error signal. In one embodiment of the phase detector, the logic unit analyzes the signs of the two digital signals and then accordingly adds or subtracts the I and Q signals to generate the phase-error signal. In another embodiment, the logic unit determines the magnitude of the phase-error signal by finding the difference in magnitudes of the two digital signals and constructing a phase-error signal proportional to this difference. The logic unit then determines the sign of the phase-error signal by analyzing the signs of the I and Q digital signals. The logic unit thus uses simple arithmetic operations to generate the phase-error signal, thereby reducing the complexity and cost of the phase detector.
摘要翻译： 一种相位检测器，使用简单的算术运算来测量DQPSK数字通信接收机的载波恢复机制中的相位误差。 载波恢复机制是提供通信系统的发射机和接收机中的振荡器之间的同步的反馈回路; 相位检测器测量与该同步的偏差，并产生在反馈环路中使用的相位误差信号以使振荡器同步。 为了执行该测量，相位检测器将接收的信号作为输入，并将其与接收机中的本地振荡器进行比较以产生两个数字信号：接收信号的同相（I）和正交相（Q）分量。 这些信号是逻辑单元的输入，它使用这两个信号来确定相位误差信号。 在相位检测器的一个实施例中，逻辑单元分析两个数字信号的符号，然后相应地增加或减去I和Q信号以产生相位误差信号。 在另一个实施例中，逻辑单元通过找到两个数字信号的幅度差异来构造相位误差信号的大小，并且构成与该差成比例的相位误差信号。 逻辑单元然后通过分析I和Q数字信号的符号来确定相位误差信号的符号。 因此，逻辑单元使用简单的算术运算来产生相位误差信号，从而降低了相位检测器的复杂性和成本。
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