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公开(公告)号：US10511316B2
公开(公告)日：2019-12-17
申请号：US16053455
申请日：2018-08-02
Applicant: Analog Devices Global Unlimited Company
Inventor： Rares Bodnar , Roberto S. Maurino , Christopher Peter Hurrell , Asif Ahmad
Abstract: A stage, suitable for use in and analog to digital converter or a digital to analog converter, comprises a plurality of slices. The slices can be operated together to form a composite output having reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This allows a fast conversion to be achieved without loss of noise performance. The slices can be sub-divided to reduce scaling mismatch between the most significant bit and the least significant bit. A shuffling scheme is implemented that allows shuffling to occur between the sub-sections of the slices without needing to implement a massively complex shuffler.
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公开(公告)号：US10509104B1
公开(公告)日：2019-12-17
申请号：US16102113
申请日：2018-08-13
Applicant: Analog Devices Global Unlimited Company
Inventor： Pablo Cruz Dato
Abstract: Apparatus and methods for synchronization of multiple semiconductor dies are provided herein. In certain implementations, a reference clock signal is distributed to two or more semiconductor dies that each include at least one data converter. The two or more dies include a master die that generates a data converter synchronization signal, and at least one slave die that processes the data converter synchronization signal to align timing of data conversion operations across the dies, for instance, to obtain a high degree of timing coherence for digital sampling. In certain implementations, the dies correspond to radar chips of a radar system, and the data converter synchronization signal corresponds to an analog-to-digital converter (ADC) synchronization signal. Additionally, the master radar chip generates a ramp synchronization signal to synchronize transmission sequencing across the radar chips and/or to provide phase alignment of ADC clock signals.
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23.发明申请公开(公告)号：US20190339727A1
公开(公告)日：2019-11-07
申请号：US15969204
申请日：2018-05-02
Applicant: Analog Devices Global Unlimited Company
Inventor： Sriram GANESAN , Amit Kumar SINGH , Nilanjan PAL , Nitish KUTTAN
IPC: G05F1/46 , G11C11/417 , G01R19/00
Abstract: Methods, systems and circuits for controlling the power available to the load, by reducing the power available to the load, and additionally or alternatively, limiting the current available by pre-establishing a maximum reference current. The reference current is compared to the actual or estimated current drawn by the load or part of the load. The comparison result is used to control a device or switch which disconnects the power supply or power supply regulator, whether connected directly to the load or connected via voltage dropping device, to one or more or a plurality of the load blocks when the maximum current is exceeded.
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公开(公告)号：US10461770B2
公开(公告)日：2019-10-29
申请号：US16015585
申请日：2018-06-22
Applicant: Analog Devices Global Unlimited Company
Inventor： Avinash Gutta , Venkata Aruna Srikanth Nittala
Abstract: Techniques for a configurable analog-to-digital converter filter to ameliorate transfer function peaking or frequency response issues are provided. In an example, a front-end circuit of a processing circuit can include a resistor-capacitor filter including at least two capacitors and a switch circuit. The resistor-capacitor filter can couple an input analog signal to the processing circuit. The switch circuit can couple to a first capacitor of the at least two capacitors, and can selectively place a terminal of the first capacitor at a selected one of a plurality of distinct nodes of the resistor-capacitor filter to configure the circuit to address the peaking or frequency response issue.
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公开(公告)号：US10454488B1
公开(公告)日：2019-10-22
申请号：US15994112
申请日：2018-05-31
Applicant: Analog Devices Global Unlimited Company
Inventor： Sandeep Monangi
Abstract: Various examples are directed to a variable speed comparator circuit comprising a first comparator, a second comparator, and a third comparator and a logic circuit. The first comparator may be configured to generate a first comparator output using a first input and a second input. The second comparator may be configured to generate a second comparator output using the first input and the second input. The third comparator may be configured to generate a third comparator output using the first input and the second input. A propagation delay of the second comparator may be less than a propagation delay of the first comparator. Also, a propagation delay of the third comparator may be less than the propagation delay of the second comparator. The second comparator may have an input offset relative to the third comparator. The logic circuit may be configured to determine that the second comparator output and the third comparator output are not equivalent and set a comparator circuit output to the first comparator output.
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Patent Agency Ranking
公开(公告)号：US20190319011A1
公开(公告)日：2019-10-17
申请号：US16366476
申请日：2019-03-27
Applicant: ANALOG DEVICES GLOBAL UNLIMITED COMPANY
Inventor： Rigan McGeehan , Cillian Burke , Alan J. O'Donnell
IPC: H01L25/065 , H01L21/304 , H01L21/78 , H01L23/00 , H01L25/00
Abstract: An integrated device package is disclosed. The package can include a carrier and an integrated device die having a front side and a back side. A mounting structure can serve to mount the back side of the integrated device die to the carrier. The mounting structure can comprise a first layer over the carrier and a second element between the back side of the integrated device die and the first layer. The first layer can comprise a first insulating material that adheres to the carrier, and the second element can comprise a second insulating material.
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公开(公告)号：US20190305785A1
公开(公告)日：2019-10-03
申请号：US15942119
申请日：2018-03-30
Applicant: Analog Devices Global Unlimited Company
Inventor： Vamshi Krishna Chillara , Declan M. Dalton , Pablo Cruz Dato
Abstract: Aspects of this disclosure relate to reducing settling time of a ramp signal in a phase-locked loop. An offset signal can be applied to adjust an input signal provided to an integrator of a loop filter of the phase-locked loop to cause the settling time to be reduced. Disclosed methods of reducing settling time of a ramp signal can improve settling time of a ramp signal independent of the profile of the ramp signal.
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公开(公告)号：US20190296726A1
公开(公告)日：2019-09-26
申请号：US15926323
申请日：2018-03-20
Applicant: Analog Devices Global Unlimited Company
Inventor： Turusan Kolcuoglu , Huseyin Kayahan , Yusuf Alperen Atesal
IPC: H03K17/04 , H04B1/44 , H03K17/693
Abstract: Apparatus and methods for biasing radio frequency (RF) switches to achieve fast switching are disclosed herein. In certain configurations, a switch bias circuit generates a switch control voltage for turning on or off a switch that handles RF signals. The switch bias circuit provides the switch control voltage to a control input of the switch by way of a resistor. Additionally, the switch bias circuit pulses the switch control voltage when turning on or off the switch to thereby shorten switching time. Thus, the switch can be turned on or off quickly, which allows the switch to be available for use soon after the state of the switch has been changed.
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公开(公告)号：US20190293689A1
公开(公告)日：2019-09-26
申请号：US16003701
申请日：2018-06-08
Applicant: Analog Devices Global Unlimited Company
Inventor： Boris Lerner , Yogesh Jayaraman Sharma , Sefa Demirtas , Jochen Schmitt , Paul Blanchard , Arthur J. Kalb , Harvey Weinberg , Jonathan Ephraim David Hurwitz
Abstract: Embodiments of the present disclosure provide mechanisms for measuring currents flowing in one or more conductor wires. The mechanisms are based on using magnetic sensor pairs arranged within a housing with an opening for the wires, where each magnetic sensor pair can generate a pair of signals indicative of magnetic fields in two different directions. The outputs of the sensor pairs can be used to derive a measure of current(s) flowing through the one or more wires. The use of magnetic sensor pairs that can measure magnetic field in two different directions may enable simultaneous current measurement in multiple wires placed within the opening, improve accuracy of current measurements while relaxing requirements for precise control of the placement of the wire(s), reduce the impact of stray magnetic interference, and enable both AC and DC measurements.
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公开(公告)号：US20190280705A1
公开(公告)日：2019-09-12
申请号：US15916009
申请日：2018-03-08
Applicant: Analog Devices Global Unlimited Company
Inventor： Rares BODNAR , Asif AHMAD , Christopher Peter HURRELL
Abstract: A stage, suitable for use in an analog to digital converter or a digital to analog converter, can have a plurality of slices that can be operated together to form a composite output. The stage can have reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This feature allows a fast conversion to be achieved without loss of noise performance.
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