公开(公告)号：US20240162092A1

公开(公告)日：2024-05-16

申请号：US18489999

申请日：2023-10-19

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation ,  MITSUBOSHI DIAMOND INDUSTRIAL CO., LTD.

Inventor： Yuji NAGUMO ,  Masashi UECHA ,  Masaru OKUDA ,  Masatake NAGAYA ,  Mitsuru KITAICHI ,  Akira MORI ,  Naoya KIYAMA ,  Masakazu TAKEDA

IPC: H01L21/784 ,  H01L21/3205

CPC classification number: H01L21/784 ,  H01L21/32051

Abstract: A manufacturing method of a semiconductor device includes: forming a plurality of element structures in a form of matrix on a first surface of a semiconductor wafer; forming a crack extending in a thickness direction of the semiconductor wafer along a boundary between the element structures adjacent to each other by pressing a pressing member against a second surface of the semiconductor wafer opposite to the first surface along the boundary; and dividing the semiconductor wafer along the boundary by pressing a dividing member against the semiconductor wafer on a first surface side along the boundary.

公开(公告)号：US11967774B2

公开(公告)日：2024-04-23

申请号：US17833952

申请日：2022-06-07

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation

Inventor： Masato Kohtani

IPC: H01Q3/34 ,  H01Q1/32 ,  H01Q3/26 ,  H01Q21/00 ,  H01Q21/06

CPC classification number: H01Q3/34 ,  H01Q1/3233 ,  H01Q3/2617 ,  H01Q21/065

Abstract: An antenna array for a high frequency device includes a plurality of antenna elements used for a radar device and arranged in a two-dimensional array in a predetermined area. The plurality of antenna elements includes grouped on-elements and single on-elements with specific distance for grating lobe cancellation, each of them is electrically connected to a phase shifter. The on-elements are arranged such that density of the on-elements at a center portion in the two-dimensional array is high and density of the on-elements at four corners in the two-dimensional array is low.

公开(公告)号：US20240128371A1

公开(公告)日：2024-04-18

申请号：US18472312

申请日：2023-09-22

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation

Inventor： YUICHI MORI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/0692 ,  H01L29/4236 ,  H01L29/66734

Abstract: A semiconductor device includes: a semiconductor substrate having a first main surface and a second main surface, in which a first semiconductor region, a second semiconductor region, and a third semiconductor region are arranged in this order in a thickness direction of the semiconductor substrate. The third semiconductor region is exposed from the first main surface. Trench gates are extended from the first main surface to reach the first semiconductor region beyond the third semiconductor region and the second semiconductor region. The trench gates are spaced from each other in a first direction. A part of the semiconductor substrate located between the trench gates adjacent to each other in the first direction includes a trunk portion extending along a second direction orthogonal to the first direction and a branch portion protruding from the trunk portion.

公开(公告)号：US20240072143A1

公开(公告)日：2024-02-29

申请号：US18453654

申请日：2023-08-22

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation

Inventor： Fumihito TACHIBANA

IPC: H01L29/423 ,  H01L29/16

CPC classification number: H01L29/4236 ,  H01L29/1608 ,  H01L29/7397

Abstract: A semiconductor device includes a semiconductor substrate having a trench adjacent to an upper surface, a gate insulating film inside the trench, a gate electrode on the gate insulating film inside the trench, and an interlayer insulating film covering the gate electrode inside the trench. The semiconductor substrate has a connection surface that connects between the upper surface of the semiconductor substrate and a side surface of the trench and is located below the upper surface of the semiconductor substrate. An upper surface of the gate insulating film is located below the connection surface. An upper surface of the interlayer insulating film is located below the upper surface of the gate insulating film. A metal film is disposed to cover the upper surface of the semiconductor substrate, the connection surface, the upper surface of the gate insulating film, and the upper surface of the interlayer insulating film.

公开(公告)号：US20240061019A1

公开(公告)日：2024-02-22

申请号：US18448668

申请日：2023-08-11

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation

Inventor： Shotaro WADA ,  Yoshikazu FURUTA ,  Tomohiro NEZUKA

IPC: G01R15/14

CPC classification number: G01R15/146

Abstract: A current sensor includes a current detection unit, a relay, a relay control unit, and a resistance value correction circuit. The current detection unit detects a detection target current based on a terminal voltage of a shunt resistor located in series with a path through which the detection target current flows and a detection resistance value for current detection corresponding to a resistance value of the shunt resistor. The relay is located in series with the path through which the detection target current flows. The relay control unit controls the relay to be turned on or off. The resistance value correction circuit calculates the resistance value of the shunt resistor as a calculated resistance value and corrects the detection resistance value based on the calculated resistance value.

公开(公告)号：US11899044B2

公开(公告)日：2024-02-13

申请号：US17875547

申请日：2022-07-28

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation

Inventor： Tomohiro Nezuka ,  Yoshikazu Furuta ,  Shotaro Wada

IPC: G01R33/04 ,  G01R15/14 ,  G01R27/02 ,  G01R19/00 ,  G01R15/24 ,  G01R1/07 ,  G01R33/02 ,  G01C17/30 ,  G01C17/28 ,  G01C17/38

CPC classification number: G01R15/146 ,  G01R1/071 ,  G01R15/242 ,  G01R15/246 ,  G01R19/0092 ,  G01R27/02 ,  G01R33/02 ,  G01R33/04 ,  G01R33/045 ,  G01C17/28 ,  G01C17/30 ,  G01C17/38

Abstract: A current sensor for a detection target current using a shunt resistor includes: a resistance value correction circuit having a correction resistor; a signal application unit that applies an alternating current signal to a series circuit of the shunt resistor and the correction resistor; a voltage detection unit that detects terminal voltages of the shunt resistor and the correction resistor; and a correction unit that calculates a resistance value of the shunt resistor and corrects the resistance value for detection; and a power supply circuit having a first power supply generation unit that generates a first power supply of the signal application unit from an input power supply of an outside; and a second power supply generation unit that generates a second power supply of the voltage detection unit.

公开(公告)号：US20240047213A1

公开(公告)日：2024-02-08

申请号：US18362004

申请日：2023-07-31

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation

Inventor： Takashi OKAWA ,  Kenta WATANABE

IPC: H01L21/265 ,  H01L29/66 ,  H01L21/324

CPC classification number: H01L21/26553 ,  H01L29/66712 ,  H01L21/3245

Abstract: A method of manufacturing a semiconductor device includes: injecting an inert element or an electron beam into a GaN-based semiconductor substrate; implanting magnesium into the GaN-based semiconductor substrate; and performing a heat treatment after the injecting and the implanting. A first implantation range of inert element or electron beam and a second implantation range of magnesium overlap with each other. A reference depth Dref (nm) calculated using a formula of Dref=D1+140 and a deepest injection depth D1 (nm) in the injecting is deeper than a deepest implantation depth D2 (nm) in the implanting. After the heat treatment, a concentration of magnesium decreases toward a deeper side at a predetermined decrease rate at a position of the reference depth Dref. The predetermined decrease rate is smaller than a decrease rate at which a concentration of magnesium becomes 1/10 per depth of 300 nm.

公开(公告)号：US11881407B2

公开(公告)日：2024-01-23

申请号：US17463243

申请日：2021-08-31

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation ,  DISCO Corporation

Inventor： Masatake Nagaya ,  Teruaki Kumazawa ,  Yuji Nagumo ,  Kazuya Hirata ,  Asahi Nomoto

IPC: H01L21/78 ,  H01L21/268 ,  H01L21/02

CPC classification number: H01L21/2683 ,  H01L21/02447 ,  H01L21/7813

Abstract: A method of manufacturing a chip formation wafer includes: forming an epitaxial film on a first main surface of a silicon carbide wafer to provide a processed wafer having one side adjacent to the epitaxial film and the other side; irradiating a laser beam into the processed wafer from the other side of the processed wafer so as to form an altered layer along a surface direction of the processed wafer; and separating the processed wafer with the altered layer as a boundary into a chip formation wafer having the one side of the processed wafer and a recycle wafer having the other side of the processed wafer. The processed wafer has a beveling portion at an outer edge portion of the processed wafer, and an area of the other side is larger than an area of the one side in the beveling portion.

公开(公告)号：US20240021681A1

公开(公告)日：2024-01-18

申请号：US18350898

申请日：2023-07-12

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation

Inventor： TATSUJI NAGAOKA ,  HIROKI MIYAKE

IPC: H01L29/40 ,  H01L29/868 ,  H01L29/872 ,  H01L29/06

CPC classification number: H01L29/407 ,  H01L29/868 ,  H01L29/872 ,  H01L29/0615

Abstract: A semiconductor device includes a semiconductor substrate having an element region and a peripheral region. The semiconductor substrate includes a high-concentration layer, a drift layer, and a low-concentration layer. The high-concentration layer extends from the element region to the peripheral region, and is in contact with a lower electrode. The high-concentration layer has a thin plate portion and a thick plate portion. The drift layer is in contact with the upper surface of the thick plate portion. The low-concentration layer extends from the element region to the peripheral region, and is in contact with an upper surface of the thin plate portion and a side surface of a stepped portion at a boundary between the thin plate portion and the thick plate portion. A half or more of a quadrilateral region in a cross section of the semiconductor substrate is not depleted.

公开(公告)号：US20240021464A1

公开(公告)日：2024-01-18

申请号：US18350251

申请日：2023-07-11

Applicant: DENSO CORPORATION ,  TOYOTA JIDOSHA KABUSHIKI KAISHA ,  MIRISE Technologies Corporation

Inventor： Hiroaki FUJIBAYASHI ,  Hirotaka MORI ,  Takayuki SATOMURA ,  Shigeyuki TAKAGI

IPC: H01L21/687 ,  C23C16/44 ,  C23C16/458 ,  C23C16/455

CPC classification number: H01L21/68785 ,  C23C16/4412 ,  C23C16/4584 ,  C23C16/4586 ,  C23C16/45557

Abstract: A semiconductor wafer manufacturing apparatus includes a reaction chamber, a reactant gas supply pipe and a reactant gas discharge pipe communicated with the reaction chamber, a rotating device having a cylindrical member, a lid member disposed on one end portion of the cylindrical member, a heating device disposed in a hollow chamber that is a space surrounded by the cylindrical member and the lid member, an inert gas supply pipe and an inert gas discharge pipe communicated with the hollow chamber, and a controller. The controller is configured to adjust an amount of an inert gas discharged from the inert has discharge pipe such that a pressure in the hollow chamber is higher than a pressure in the reaction chamber and equal to or lower than a pressure of a minimum closing portion of the lid member.