公开(公告)号：US12295145B2

公开(公告)日：2025-05-06

申请号：US18446586

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chenchen Jacob Wang ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Chi On Chui

IPC: H10B61/00 ,  H01L21/02 ,  H01L29/24 ,  H10N50/01

Abstract: In an embodiment, a semiconductor device includes a first dielectric layer over a substrate and a first access transistor and a second access transistor in a memory cell of a memory array, the first access transistor and the second access transistor each including a bottom electrode in the first dielectric layer, a conductive gate in a second dielectric layer, where the second dielectric layer is over the bottom electrode and the first dielectric layer, a channel region extending through the conductive gate to contact the bottom electrode, and a top electrode over the channel region.

公开(公告)号：US12243932B2

公开(公告)日：2025-03-04

申请号：US18358377

申请日：2023-07-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Te-Yang Lai ,  Chun-Yen Peng ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/51 ,  H01L29/78

Abstract: Negative capacitance field-effect transistor (NCFET) and ferroelectric field-effect transistor (FE-FET) devices and methods of forming are provided. The gate dielectric stack of the NCFET and FE-FET devices includes a non-ferroelectric interfacial layer formed over the semiconductor channel, and a ferroelectric gate dielectric layer formed over the interfacial layer. The ferroelectric gate dielectric layer is formed by inserting dopant-source layers in between amorphous high-k dielectric layers and then converting the alternating sequence of dielectric layers to a ferroelectric gate dielectric layer by a post-deposition anneal (PDA). The ferroelectric gate dielectric layer has adjustable ferroelectric properties that may be varied by altering the precisely-controlled locations of the dopant-source layers using ALD/PEALD techniques. Accordingly, the methods described herein enable fabrication of stable NCFET and FE-FET FinFET devices that exhibit steep subthreshold slopes.

公开(公告)号：US12243925B2

公开(公告)日：2025-03-04

申请号：US17869430

申请日：2022-07-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Cheng-Lung Hung ,  Chi On Chui

IPC: H01L29/423 ,  H01L21/28 ,  H01L29/06 ,  H01L29/10 ,  H01L29/49 ,  H01L29/78

Abstract: A device includes a first nanostructure; a second nanostructure over the first nanostructure; a first high-k gate dielectric around the first nanostructure; a second high-k gate dielectric around the second nanostructure; and a gate electrode over the first and second high-k gate dielectrics. A portion of the gate electrode between the first nanostructure and the second nanostructure comprises: a first p-type work function metal; a barrier material over the first p-type work function metal; and a second p-type work function metal over the barrier material, the barrier material physically separating the first p-type work function metal from the second p-type work function metal.

公开(公告)号：US12243573B2

公开(公告)日：2025-03-04

申请号：US18343972

申请日：2023-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chenchen Wang ,  Sai-Hooi Yeong ,  Chi On Chui ,  Yu-Ming Lin

IPC: H01L29/78 ,  G11C11/22 ,  H01L29/51

Abstract: A semiconductor device including a capacitor, with a memory film isolating a first electrode from a contact, formed over a transistor and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate stack over a semiconductor substrate; a capacitor over the gate stack, the capacitor including a first electrode extending along a top surface of the gate stack, the first electrode being U-shaped; a first ferroelectric layer over the first electrode; and a second electrode over the first ferroelectric layer, a top surface of the second electrode being level with a top surface of the first ferroelectric layer, and the top surface of the first ferroelectric layer and the top surface of the second electrode being disposed further from the semiconductor substrate than a topmost surface of the first electrode.

公开(公告)号：US20250063736A1

公开(公告)日：2025-02-20

申请号：US18936362

申请日：2024-11-04

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Chi On Chui ,  Sheng-Chen Wang

IPC: H10B51/20 ,  G11C5/06 ,  G11C11/22 ,  H01L21/28 ,  H01L29/66 ,  H10B43/10 ,  H10B43/20 ,  H10B51/10 ,  H10B53/20

Abstract: In an embodiment, a device includes: a first word line over a substrate, the first word line including a first conductive material; a first bit line intersecting the first word line; a first memory film between the first bit line and the first word line; and a first conductive spacer between the first memory film and the first word line, the first conductive spacer including a second conductive material, the second conductive material having a different work function than the first conductive material, the first conductive material having a lower resistivity than the second conductive material.

公开(公告)号：US20250006560A1

公开(公告)日：2025-01-02

申请号：US18828663

申请日：2024-09-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chieh-Ping Wang ,  Ting-Gang Chen ,  Bo-Cyuan Lu ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L21/8234 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/762 ,  H01L21/764 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78

Abstract: A method for forming a semiconductor device includes: forming a gate structure over a fin, where the fin protrudes above a substrate; forming an opening in the gate structure; forming a first dielectric layer along sidewalls and a bottom of the opening, where the first dielectric layer is non-conformal, where the first dielectric layer has a first thickness proximate to an upper surface of the gate structure distal from the substrate, and has a second thickness proximate to the bottom of the opening, where the first thickness is larger than the second thickness; and forming a second dielectric layer over the first dielectric layer to fill the opening, where the first dielectric layer is formed of a first dielectric material, and the second dielectric layer is formed of a second dielectric material different from the first dielectric material.

公开(公告)号：US12176401B2

公开(公告)日：2024-12-24

申请号：US18446681

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsin-Yi Lee ,  Weng Chang ,  Chi On Chui

IPC: H01L29/00 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming epitaxial source/drain regions on opposite sides of the dummy gate stack, removing the dummy gate stack to form a trench, depositing a gate dielectric layer extending into the trench, and depositing a work-function layer over the gate dielectric layer. The work-function layer comprises a seam therein. A silicon-containing layer is deposited to fill the seam. A planarization process is performed to remove excess portions of the silicon-containing layer, the work-function layer, and the gate dielectric layer. Remaining portions of the silicon-containing layer, the work-function layer, and the gate dielectric layer form a gate stack.

公开(公告)号：US12171102B2

公开(公告)日：2024-12-17

申请号：US17567269

申请日：2022-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Chi On Chui ,  Sheng-Chen Wang

IPC: H10B51/20 ,  G11C5/06 ,  G11C11/22 ,  H01L21/28 ,  H01L29/66 ,  H10B43/10 ,  H10B43/20 ,  H10B51/10 ,  H10B53/20

Abstract: In an embodiment, a device includes: a first word line over a substrate, the first word line including a first conductive material; a first bit line intersecting the first word line; a first memory film between the first bit line and the first word line; and a first conductive spacer between the first memory film and the first word line, the first conductive spacer including a second conductive material, the second conductive material having a different work function than the first conductive material, the first conductive material having a lower resistivity than the second conductive material.

公开(公告)号：US20240397730A1

公开(公告)日：2024-11-28

申请号：US18790277

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Chi On Chui

IPC: H10B53/30 ,  H01L29/66 ,  H01L29/78

Abstract: A semiconductor device includes a first dielectric layer, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, an ferroelectric random-access memory (FeRAM) cell in the second dielectric layer, a third dielectric layer over the second dielectric layer, and a second conductive feature in the third dielectric layer, the second conductive feature being electrically coupled to the top electrode. The FeRAM cell includes a bottom electrode contacting the first conductive feature, a ferroelectric material layer completely covering an upper surface of the bottom electrode, and a top electrode on the ferroelectric material layer.

公开(公告)号：US20240395907A1

公开(公告)日：2024-11-28

申请号：US18790476

申请日：2024-07-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wen-Ju Chen ,  Chung-Ting Ko ,  Ya-Lan Chang ,  Ting-Gang Chen ,  Tai-Chun Huang ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/033 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/78

Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.